6 files changed, 46 insertions, 15 deletions

diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index decaaff..5559b26 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -404,9 +404,9 @@ attain the greatest code size reduction.
 
 [[reg-based-ldnstr]]
 include::images/wavedrom/reg-based-ldnstr.adoc[]
-.Compressed, register-Based Loads and Stores
+.Compressed, register-based load and stores
 image::image_placeholder.png[]
-(((compressed, regoster-based load and store)))
+(((compressed, register-based load and store)))
 
 These instructions use the CL format.
 
@@ -450,6 +450,13 @@ offset[7:6] & src & C0 +
 C.FSW& offset[5:3] & base & offset[2latexmath:[$\vert$]6] & src & C0 +
 C.FSD& offset[5:3] & base & offset[7:6] & src & C0 +
 
+[[c-cs-format-ls]]
+include::images/wavedrom/c-cs-format-ls.adoc[]
+.Compressed, CS format load and store
+image::image_placeholder.png[]
+(((compressed, cs-format load and store)))
+
+
 These instructions use the CS format.
 
 C.SW stores a 32-bit value in register _rs2 l'_ to memory.
@@ -499,6 +506,14 @@ C.JAL &
 offset[11latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmath:[$\vert$]6latexmath:[$\vert$]7latexmath:[$\vert$]3:1latexmath:[$\vert$]5]
 & C1 +
 
+[[c-cj-format-ls]]
+//include::images/wavedrom/c-cj-format-ls.adoc[]
+.Compressed, CJ format load and store
+image::image_placeholder.png[]
+(((compressed, cj-format load and store)))
+
+
+
 These instructions use the CJ format.
 
 C.J performs an unconditional control transfer. The offset is
diff --git a/src/counters.adoc b/src/counters.adoc
index a92b3fc..38f7ac3 100644
--- a/src/counters.adoc
+++ b/src/counters.adoc
@@ -46,7 +46,7 @@ environment should provide a means to determine the current rate
 [TIP]
 ====
 RDCYCLE is intended to return the number of cycles executed by the
-processor core, not the hart. Precisely defining what is a "core"
+processor core, not the hart. Precisely defining what is a "core" is
 difficult given some implementation choices (e.g., AMD Bulldozer).
 Precisely defining what is a "clock cycle" is also difficult given the
 range of implementations (including software emulations), but the intent
diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc
index 2762d9b..4defc62 100644
--- a/src/images/wavedrom/c-sp-load-store.adoc
+++ b/src/images/wavedrom/c-sp-load-store.adoc
@@ -4,11 +4,25 @@
 [wavedrom, , svg]
 ....
 {reg: [
-  {bits: 2, name: 'op',     type: 8, attr: 'C2'},
-  {bits: 5, name: 'imm',    type: 3, attr: ['offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']},
-  {bits: 5, name: 'rd',     type: 2, attr: ['dest ≠ 0', 'dest ≠ 0', 'dest ≠ 0', 'dest', 'dest']},
-  {bits: 1, name: 'imm',    type: 3, attr: 'offset[5]'},
-  {bits: 3, name: 'funct3', type: 8, attr: ['C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']},
+  {bits: 2, name: 'op',     type: 8, attr: ['C2','C2','C2','C2','C2']},
+  {bits: 5, name: 'imm',    type: 5, attr: ['offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']},
+  {bits: 5, name: 'rd',     type: 5, attr: ['dest ࣔ 0', 'dest ≠ 0', 'dest ≠ 0', 'dest', 'dest']},
+  {bits: 1, name: 'imm',    type: 1, attr: ['offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']},
+  {bits: 3, name: 'funct3', type: 3, attr: ['C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']},
 ], config: {bits: 16}}
 ....
 
+
+
+[wavedrom, , svg]
+....
+{reg: [
+  {bits: 1, name: 'op',     type: 8, attr: ['C2','C2','C2','C2','C2']},
+  {bits: 5, name: 'imm',    type: 2, attr: ['offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']},
+  {bits: 5, name: 'rd',     type: 3, attr: ['dest ≠ 0','dest ≠ 0','dest ≠ 0','dest','dest']},
+  {bits: 1, name: 'imm',    types:3, attr: ['offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']},
+  {bits: 4, name: 'funct3', type: 8, attr: ['C.LWSP','C.LDSP','C.LQSP','C.FLWSP','C.FLDSP']},
+], config: {bits: 16}}
+....
+
+
diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.adoc
index ea9858d..6a137b2 100644
--- a/src/images/wavedrom/counters-diag.adoc
+++ b/src/images/wavedrom/counters-diag.adoc
@@ -4,11 +4,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode', attr: 'SYSTEM',  type: 8},
-  {bits: 5,  name: 'rd',     attr: 'dest',    type: 2},
-  {bits: 3,  name: 'func3',  attr: 'CSRRS',   type: 8},
-  {bits: 5,  name: 'rs1',    attr: 0,         type: 8},
-  {bits: 12, name: 'csr',    attr: ['RDCYCLE[H]', 'RDTIME[H]', 'RDINSTRET[H]'], type: 4},
+  {bits: 7,  name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM'], type: 8},
+  {bits: 5,  name: 'rd',     attr: ['5','dest','dest','dest'],  type: 2},
+  {bits: 3,  name: 'func3',  attr: ['3','CSRRS','CSRRS','CSRRS'],  type: 8},
+  {bits: 5,  name: 'rs1',    attr: ['5','0','0','0'], type: 8},
+  {bits: 12, name: 'csr',    attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]'], type: 4},
 ]}
 ....
 
diff --git a/src/images/wavedrom/sp-base-ls-2.adoc b/src/images/wavedrom/sp-base-ls-2.adoc
index a5c05f0..69ee285 100644
--- a/src/images/wavedrom/sp-base-ls-2.adoc
+++ b/src/images/wavedrom/sp-base-ls-2.adoc
@@ -2,10 +2,12 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['C2','C2','C2','C2','C2']},
+  {bits: 1, name: 'op',     type: 8, attr: ['C2','C2','C2','C2','C2']},
   {bits: 5, name: 'rs2',    type: 4, attr: ['src', 'src', 'src', 'src', 'src']},
-  {bits: 6, name: 'imm',    type: 3, attr: ['offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]', 'offset[5:3|8:6]']},
+  {bits: 6, name: 'imm',    type: 3, attr: ['offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']},
 ], config: {bits: 16}}
 ....
 
+
+
diff --git a/src/riscv-isa-unpr-conv-review.pdf b/src/riscv-isa-unpr-conv-review.pdf
index e4a310e..0ecaa33 100644
--- a/src/riscv-isa-unpr-conv-review.pdf
+++ b/src/riscv-isa-unpr-conv-review.pdf