diff options
| -rw-r--r-- | src/images/wavedrom/rv64i-addiw.adoc | 27 | ||||
| -rw-r--r-- | src/images/wavedrom/rv64i-slli.adoc | 11 | ||||
| -rw-r--r-- | src/images/wavedrom/rv64i-slliw.adoc | 12 | ||||
| -rw-r--r-- | src/rv64.adoc | 7 |
4 files changed, 28 insertions, 29 deletions
diff --git a/src/images/wavedrom/rv64i-addiw.adoc b/src/images/wavedrom/rv64i-addiw.adoc deleted file mode 100644 index 3cbd38a..0000000 --- a/src/images/wavedrom/rv64i-addiw.adoc +++ /dev/null @@ -1,27 +0,0 @@ -//rv64i-addiw - -[wavedrom, ,] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI', 'SLLIW', 'SRLIW', 'SRAIW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src', 'src', 'src', 'src'], type: 4}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3}, - {bits: 1, name: '[5]', attr: ['1', 'shamt[5]', 'shamt[5]', 'shamt[5]', '0', '0', '0'], type: 3}, - {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000', '000000', '000000', '000000'], type: 8} -], config: {fontsize: 9}} -.... - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-IMM-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['SLLIW', 'SRLIW', 'SRAIW'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src', type: 4}, -// {bits: 5, name: 'imm[4:0]', attr: 'shamt[4:0]', type: 3}, -// {bits: 1, name: '[5]', attr: 0}, -// {bits: 6, name: 'imm[11:6]', attr: [0, 0, 32], type: 8} -//]} -//....
\ No newline at end of file diff --git a/src/images/wavedrom/rv64i-slli.adoc b/src/images/wavedrom/rv64i-slli.adoc new file mode 100644 index 0000000..57eff4b --- /dev/null +++ b/src/images/wavedrom/rv64i-slli.adoc @@ -0,0 +1,11 @@ +[wavedrom, ,] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, + {bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]'], type: 3}, + {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8} +]} +.... diff --git a/src/images/wavedrom/rv64i-slliw.adoc b/src/images/wavedrom/rv64i-slliw.adoc new file mode 100644 index 0000000..e4cda61 --- /dev/null +++ b/src/images/wavedrom/rv64i-slliw.adoc @@ -0,0 +1,12 @@ +[wavedrom, ,] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32'], type: 8}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW'], type: 8}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3}, + {bits: 1, name: '[5]', attr: ['1', '0', '0', '0'], type: 3}, + {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8} +]} +.... diff --git a/src/rv64.adoc b/src/rv64.adoc index cf6911c..f33bf8c 100644 --- a/src/rv64.adoc +++ b/src/rv64.adoc @@ -50,8 +50,8 @@ immediate to register _rs1_ and produces the proper sign-extension of a writes the sign-extension of the lower 32 bits of register _rs1_ into register _rd_ (assembler pseudoinstruction SEXT.W). -include::images/wavedrom/rv64i-addiw.adoc[] -[[rv64i-addiw]] +include::images/wavedrom/rv64i-slli.adoc[] +[[rv64i-slli]] //.RV64I register-immediate (descr ADDIW) instructions Shifts by a constant are encoded as a specialization of the I-type @@ -67,6 +67,9 @@ copied into the vacated upper bits). (((RV64I, SRLIW))) (((RV64I, RV64I-only))) +include::images/wavedrom/rv64i-slliw.adoc[] +[[rv64i-slliw]] + SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with |