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| author | Andrew Waterman <andrew@sifive.com> | 2019-01-17 14:57:25 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-01-17 15:00:19 -0800 |
| commit | b6527e1b18eb0110007dc24794addccb04bebc41 (patch) | |
| tree | de23094e6cccabd5b9d1ea14258ae1956f96d942 /src | |
| parent | 8a55333c73e64a02a00dde0c344fdabeaf0ccc7b (diff) | |
| download | riscv-isa-manual-b6527e1b18eb0110007dc24794addccb04bebc41.zip riscv-isa-manual-b6527e1b18eb0110007dc24794addccb04bebc41.tar.gz riscv-isa-manual-b6527e1b18eb0110007dc24794addccb04bebc41.tar.bz2 | |
JALR is not allowed within LR/SC sequences
This used to be the case, until an editing error several years ago.
Diffstat (limited to 'src')
| -rw-r--r-- | src/a.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -150,7 +150,7 @@ comprise at most 16 integer instructions placed sequentially in memory. For the sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and SC instructions can only contain other instructions from the base ``I'' instruction set, excluding -loads, stores, backward jumps or taken backward branches, FENCE, +loads, stores, backward jumps or taken backward branches, JALR, FENCE, FENCE.I, and SYSTEM instructions. The code to retry a failing LR/SC sequence can contain backward jumps and/or branches to repeat the LR/SC sequence, but otherwise has the same constraints. The SC must |