Clean up naming and define G = IMAFDZicsr_Zifencei

Closes #266.

3 files changed, 18 insertions, 22 deletions

diff --git a/src/gmaps.tex b/src/gmaps.tex
index a00ce65..ddd61b8 100644
--- a/src/gmaps.tex
+++ b/src/gmaps.tex
@@ -2,8 +2,8 @@
 
 One goal of the RISC-V project is that it be used as a stable software
 development target.  For this purpose, we define a combination of a
-base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD) as
-a ``general-purpose'' ISA, and we use the abbreviation G for the IMAFD
+base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, Zifencei) as
+a ``general-purpose'' ISA, and we use the abbreviation G for the IMAFDZicsr\_Zifencei
 combination of instruction-set extensions.    This chapter presents
 opcode maps and instruction-set listings for RV32G and RV64G.
 
diff --git a/src/intro.tex b/src/intro.tex
index 7448425..b95c6b3 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -326,9 +326,7 @@ single-precision computational instructions, and single-precision
 loads and stores.  The standard double-precision floating-point
 extension, denoted by ``D'', expands the floating-point registers, and
 adds double-precision computational instructions, loads, and stores.
-An integer base plus these four standard extensions (``IMAFD'') is
-given the abbreviation ``G'' and provides a general-purpose scalar
-instruction set.  The standard ``C'' compressed instruction extension
+The standard ``C'' compressed instruction extension
 provides narrower 16-bit forms of common instructions.
 
 Beyond the base integer ISA and the standard GC extensions, we believe
@@ -536,7 +534,7 @@ support experimentation and larger instruction-set extensions.
 Although our encoding convention required a tighter encoding of the
 core RISC-V ISA, this has several beneficial effects.
 
-An implementation of the standard G ISA need only hold the
+An implementation of the standard IMAFD ISA need only hold the
 most-significant 30 bits in instruction caches (a 6.25\% saving).  On
 instruction cache refills, any instructions encountered with either
 low bit clear should be recoded into illegal 30-bit instructions
diff --git a/src/naming.tex b/src/naming.tex
index f3e9ed0..661e50f 100644
--- a/src/naming.tex
+++ b/src/naming.tex
@@ -35,7 +35,7 @@ Any RISC-V instruction-set variant can be succinctly described by
 concatenating the base integer prefix with the names of the included
 extensions, e.g., ``RV64IMAFD''.
 
-We have also defined an abbreviation ``G'' to represent the ``IMAFD''
+We have also defined an abbreviation ``G'' to represent the ``IMAFDZicsr\_Zifencei''
 base and extensions, as this is intended to represent our standard
 general-purpose ISA.
 
@@ -58,15 +58,11 @@ loss of backwards compatibility, whereas changes in only the minor
 version number must be backwards-compatible.  For example, the
 original 64-bit standard ISA defined in release 1.0 of this manual can
 be written in full as ``RV64I1p0M1p0A1p0F1p0D1p0'', more concisely as
-``RV64I1M1A1F1D1'', or even more concisely as ``RV64G1''.  The G ISA
-can be written as ``RV64I2p0M2p0A2p0F2p0D2p0'', or more
-concisely ``RV64G2''.
+``RV64I1M1A1F1D1''.
 
-We introduced the version numbering scheme with the second release,
-which we also intend to become a permanent standard.  Hence, we define
-the default version of a standard extension to be that present at the
-time of this document, e.g., ``RV32G'' is equivalent to
-``RV32I2M2A2F2D2''.
+We introduced the version numbering scheme with the second release.  Hence, we
+define the default version of a standard extension to be the version present at that
+time, e.g., ``RV32I'' is equivalent to ``RV32I2''.
 
 \section{Underscores}
 
@@ -88,7 +84,7 @@ Chapter~\ref{chap:zifencei}; ``Zifencei2'' and ``Zifencei2p0'' name version
 
 Extensions with the ``Z'' prefix must be separated
 from other multi-letter extensions by an underscore, e.g.,
-``RV32IMACZifencei\_Zicsr''.
+``RV32IMACZicsr\_Zifencei''.
 
 \section{Non-Standard Extension Names}
 
@@ -102,16 +98,14 @@ by an underscore.  For example, an ISA with non-standard extensions
 Argle and Bargle may be named ``RV64IZifencei\_Xargle\_Xbargle''.
 
 \section{Supervisor-level Instruction-Set Extensions}
+
 Standard supervisor instruction-set extensions are defined in Volume II, but
 are named using ``S'' as a prefix, followed by an
 alphabetical name and an optional version number.
-
-Supervisor extensions must be separated from other multi-letter extensions
-by an underscore.
-
-\section{Supervisor-level Extensions}
 Non-standard extensions to the supervisor-level ISA are defined using
 the ``SX'' prefix.
+Supervisor extensions must be separated from other multi-letter extensions
+by an underscore.
 
 \section{Subset Naming Convention}
 Table~\ref{isanametable} summarizes the standardized extension names.
@@ -130,8 +124,10 @@ Integer Multiplication and Division & M \\
 Atomics & A \\
 Single-Precision Floating-Point & F \\
 Double-Precision Floating-Point & D \\
+Control and Status Register Access & Zicsr \\
+Instruction-Fetch Fence & Zifencei \\
 \hline
-General & G = IMAFD \\
+General & G = IMAFDZicsr\_Zifencei \\
 \hline
 \multicolumn{2}{|c|}{Standard Unprivileged Extensions}\\
 \hline
@@ -144,6 +140,8 @@ Transactional Memory & T \\
 Packed-SIMD Extensions & P \\
 Vector Extensions & V \\
 User-Level Interrupts & N \\
+Misaligned Atomics & Zam \\
+Total Store Ordering & Ztso \\
 \hline
 \hline
 \multicolumn{2}{|c|}{Non-Standard Unprivileged Extensions}\\