Clarified behavior of CSR instructions with respect to read and write side effects.

Closed #267

1 files changed, 48 insertions, 4 deletions

diff --git a/src/csr.tex b/src/csr.tex
index 8c1b923..f286642 100644
--- a/src/csr.tex
+++ b/src/csr.tex
@@ -78,9 +78,13 @@ For both CSRRS and CSRRC, if {\em rs1}={\tt x0}, then the instruction
 will not write to the CSR at all, and so shall not cause any of the
 side effects that might otherwise occur on a CSR write, such as
 raising illegal instruction exceptions on accesses to read-only CSRs.
-Note that if {\em rs1} specifies a register holding a zero value other
-than {\tt x0}, the instruction will still attempt to write the
-unmodified value back to the CSR and will cause any attendant side effects.
+Both CSRRS and CSRRC always read the addressed CSR and cause any read
+side effects regardless of {\em rs1} and {\em rd} fields.  Note that
+if {\em rs1} specifies a register holding a zero value other than {\tt
+  x0}, the instruction will still attempt to write the unmodified
+value back to the CSR and will cause any attendant side effects.  A
+CSRRW with {\em rs1}={\tt x0} will attempt to write zero to the
+destination CSR.
 
 The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS,
 and CSRRC respectively, except they update the CSR using an XLEN-bit
@@ -91,7 +95,47 @@ these instructions will not write to the CSR, and shall not cause any
 of the side effects that might otherwise occur on a CSR write.  For
 CSRRWI, if {\em rd}={\tt x0}, then the instruction shall not read the
 CSR and shall not cause any of the side-effects that might occur on a
-CSR read.
+CSR read.  Both CSRRSI and CSRRCI will always read the CSR and cause
+any read side-effects regardless of {\em rd} and {\em rs1} fields.
+
+\begin{table}
+  \centering
+  \begin{tabular}{|l|r|r|c|c|}
+    \hline
+    \multicolumn{5}{|c|}{Register operand} \\
+    \hline
+  Instruction &  rd &  rs1 & read CSR? & write CSR? \\
+    \hline
+    CSRRW     &  {\tt x0} &   -        &       no  &       yes \\
+    CSRRW     & !{\tt x0} &   -        &      yes  &       yes \\
+    CSRR{S/C} &        -  &   {\tt x0} &       yes &       no \\
+    CSRR{S/C} &       -   &  !{\tt x0} &       yes &      yes \\
+    \hline
+    \multicolumn{5}{|c|}{Immediate operand} \\
+    \hline
+Instruction & rd   & uimm & read CSR? & write CSR? \\
+    \hline
+   CSRRWI   &   {\tt x0} &  -   &     no    &      yes    \\
+   CSRRWI   &  !{\tt x0} &  -   &    yes    &      yes    \\ 
+ CSRR{S/C}I &       -    &  0   &    yes    &       no    \\
+ CSRR{S/C}I &       -    & !0   &    yes    &      yes    \\
+ \hline
+  \end{tabular}
+  \caption{Table showing whether a CSR instruction reads or writes a
+    given CSR.  The CSRRS and CSRRC instructions have same behavior so
+  are shown as CSRR{S/C} in Table.}
+  \label{tab:csrsideeffects}
+\end{table}
+
+Table~\ref{tab:csrsideeffects} summarizes the behavior of the CSR
+instructions with respect to whether they read and/or write the CSR.
+
+\begin{commentary}
+  The CSRs defined so far do not have any architectural side effects beyond
+  raising illegal instruction exceptions on disallowed
+  accesses.  Custom extensions might add CSRs with side effects on
+  reads and/or writes.
+\end{commentary}
 
 Some CSRs, such as the instructions-retired counter, {\tt instret},
 may be modified as side effects of instruction execution.  In these