Restate that conditional branches can raise misaligned exceptions in RVI

This is a bit redundant, since we state this at the front of the chapter.  But
since we also restate it for JAL/JALR, it's better to maintain symmetry and
restate it for branches, too.

Closes #303

h/t @benjaminselfridge

1 files changed, 12 insertions, 0 deletions

diff --git a/src/rv32.tex b/src/rv32.tex
index ced9826..a7623bb 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -946,6 +946,18 @@ allowing the branch and following instructions to be executed
 speculatively and out-of-order with respect to other code~\cite{ibmpower7}.
 \end{commentary}
 
+The conditional branch instructions will generate an
+instruction-address-misaligned exception if the target address is not
+aligned to a four-byte boundary and the branch condition evaluates
+to true.  If the branch condition evaluates to false, the
+instruction-address-misaligned exception will not be raised.
+
+\begin{commentary}
+Instruction-address-misaligned exceptions are not possible on machines
+that support extensions with 16-bit aligned instructions, such as the
+compressed instruction-set extension, C.
+\end{commentary}
+
 \section{Load and Store Instructions}
 
 RV32I is a load-store architecture, where only load and store