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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-22 14:06:30 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-02-22 14:06:30 -0800 |
| commit | e227582b162fda8453cdaa31ad7027c859e92f1f (patch) | |
| tree | 0bf26095a94155f6fa7429304833469199e1c570 /src | |
| parent | 746b4430416a048d2c051efd77e999fb69f3d508 (diff) | |
| download | riscv-isa-manual-e227582b162fda8453cdaa31ad7027c859e92f1f.zip riscv-isa-manual-e227582b162fda8453cdaa31ad7027c859e92f1f.tar.gz riscv-isa-manual-e227582b162fda8453cdaa31ad7027c859e92f1f.tar.bz2 | |
Fix mepc/sepc definitions w.r.t. IALIGN
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 10 | ||||
| -rw-r--r-- | src/supervisor.tex | 5 |
2 files changed, 4 insertions, 11 deletions
diff --git a/src/machine.tex b/src/machine.tex index e8cec03..6479ce6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1671,14 +1671,8 @@ Unlike the MIPS design, the OS can rely on holding a value in the {\tt {\tt mepc} is an XLEN-bit read/write register formatted as shown in Figure~\ref{mepcreg}. The low bit of {\tt mepc} ({\tt mepc[0]}) is -always zero. On implementations that do not support instruction-set -extensions with 16-bit instruction alignment, the two low bits ({\tt - mepc[1:0]}) are always zero. - -\begin{commentary} -The {\tt mepc} register can never hold a PC value that would cause an -instruction-address-misaligned exception. -\end{commentary} +always zero. Implementations with IALIGN=32 may additionally +hardwire {\tt mepc[1]} to zero. {\tt mepc} is a \warl\ register that must be able to hold all valid physical and virtual addresses. It need not be capable of holding all possible invalid diff --git a/src/supervisor.tex b/src/supervisor.tex index be8e5d6..e443612 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -538,9 +538,8 @@ XLEN \\ {\tt sepc} is an XLEN-bit read/write register formatted as shown in Figure~\ref{epcreg}. The low bit of {\tt sepc} ({\tt sepc[0]}) is -always zero. On implementations that do not support instruction-set -extensions with 16-bit instruction alignment, the two low bits ({\tt - sepc[1:0]}) are always zero. +always zero. Implementations with IALIGN=32 may additionally +hardwire {\tt sepc[1]} to zero. {\tt sepc} is a \warl\ register that must be able to hold all valid physical and virtual addresses. It need not be capable of holding all possible invalid |