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| author | Andrew Waterman <andrew@sifive.com> | 2017-12-12 18:31:56 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-12-12 18:31:56 -0800 |
| commit | 272d038abebe7f006ed7960b522f1e51890bb982 (patch) | |
| tree | ed92d198c36d621eac50317d058b05ab95915fa9 /src | |
| parent | f1b9ca71ffd48ed15cae6df820abeded0f607a93 (diff) | |
| download | riscv-isa-manual-272d038abebe7f006ed7960b522f1e51890bb982.zip riscv-isa-manual-272d038abebe7f006ed7960b522f1e51890bb982.tar.gz riscv-isa-manual-272d038abebe7f006ed7960b522f1e51890bb982.tar.bz2 | |
Fix inconsistency between RVC text and opcode table
The text was right and the table was wrong. C.LxSP can accept rd=x0. This
reduces decode complexity since C.FLxSP must accept rd=f0.
Diffstat (limited to 'src')
| -rw-r--r-- | src/rvc-instr-table.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex index ce7f6c5..2549a3a 100644 --- a/src/rvc-instr-table.tex +++ b/src/rvc-instr-table.tex @@ -427,7 +427,7 @@ \multicolumn{1}{c|}{uimm[5]} & \multicolumn{5}{c|}{rd$\neq$0} & \multicolumn{5}{c|}{uimm[4$\vert$9:6]} & -\multicolumn{2}{c|}{10} & C.LQSP {\em \tiny (RV128; RES, rd=0)} \\ +\multicolumn{2}{c|}{10} & C.LQSP {\em \tiny (RV128)} \\ \whline{2-17} & @@ -435,7 +435,7 @@ \multicolumn{1}{c|}{uimm[5]} & \multicolumn{5}{c|}{rd$\neq$0} & \multicolumn{5}{c|}{uimm[4:2$\vert$7:6]} & -\multicolumn{2}{c|}{10} & C.LWSP {\em \tiny (RES, rd=0)} \\ +\multicolumn{2}{c|}{10} & C.LWSP \\ \whline{2-17} & @@ -451,7 +451,7 @@ \multicolumn{1}{c|}{uimm[5]} & \multicolumn{5}{c|}{rd$\neq$0} & \multicolumn{5}{c|}{uimm[4:3$\vert$8:6]} & -\multicolumn{2}{c|}{10} & C.LDSP {\em \tiny (RV64/128; RES, rd=0)} \\ +\multicolumn{2}{c|}{10} & C.LDSP {\em \tiny (RV64/128)} \\ \whline{2-17} & |