Describe optional support for misaligned AMOs (#117)

* Fix typo

* Describe misaligned AMOs

* Improve commentary for misaligned AMO emulation

4 files changed, 49 insertions, 9 deletions

diff --git a/src/a.tex b/src/a.tex
index 5b863a1..c0e466b 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -143,10 +143,7 @@ might cause a move away from DW-CAS.
 
 The failure code with value 1 is reserved to encode an unspecified
 failure.  Other failure codes are reserved at this time, and portable
-software should only assume the failure code will be non-zero.  LR and
-SC operate on naturally-aligned 64-bit (RV64 only) or 32-bit words in
-memory.  Misaligned addresses will generate misaligned address
-exceptions.
+software should only assume the failure code will be non-zero.
 
 \begin{commentary}
 We reserve a failure code of 1 to mean ``unspecified'' so that simple
@@ -155,6 +152,19 @@ for the SLT/SLTU instructions.  More specific failure codes might be
 defined in future versions or extensions to the ISA.
 \end{commentary}
 
+The execution environment may require that the address held in {\em rs1} be
+naturally aligned to the size of the operand (i.e., eight-byte aligned for
+64-bit words and four-byte aligned for 32-bit words).  If, in such an
+execution environment, an LR or SC address is not naturally aligned,
+a misaligned address exception will be generated.
+
+If the execution environment permits misaligned LR and SC addresses, then LR
+and SC instructions using misaligned addresses execute atomically with respect
+to other accesses to the same address and of the same size.  In such
+environments, regular loads and stores using misaligned addresses also execute
+atomically with respect to other accesses to the same address and of the same
+size.
+
 \label{lrscseq}
 
 In the standard A extension, certain constrained LR/SC sequences are
@@ -318,12 +328,21 @@ value into register {\em rd}, apply a binary operator to the loaded
 value and the original value in {\em rs2}, then store the result back
 to the address in {\em rs1}. AMOs can either operate on 64-bit (RV64
 only) or 32-bit words in memory.  For RV64, 32-bit AMOs always
-sign-extend the value placed in {\em rd}. The address held in {\em
-  rs1} must be naturally aligned to the size of the operand (i.e.,
-eight-byte aligned for 64-bit words and four-byte aligned for 32-bit
-words).  If the address is not naturally aligned, a misaligned address
+sign-extend the value placed in {\em rd}.
+
+The execution environment may require that the address held in {\em rs1} be
+naturally aligned to the size of the operand (i.e., eight-byte aligned for
+64-bit words and four-byte aligned for 32-bit words).  If, in such an execution
+environment, an AMO address is not naturally aligned, a misaligned address
 exception will be generated.
 
+If the execution environment permits misaligned AMO addresses, then AMO
+instructions using misaligned addresses execute atomically with respect
+to other accesses to the same address and of the same size.  In such
+environments, regular loads and stores using misaligned addresses also execute
+atomically with respect to other accesses to the same address and of the same
+size.
+
 The operations supported are swap, integer add, logical AND, logical
 OR, logical XOR, and signed and unsigned integer maximum and minimum.
 Without ordering constraints, these AMOs can be used to implement
@@ -341,7 +360,7 @@ the destination is {\tt x0}.
 The set of AMOs was chosen to support the C11/C++11 atomic memory
 operations efficiently, and also to support parallel reductions in
 memory.  Another use of AMOs is to provide atomic updates to
-memory-mapped device registers (e..g, setting, clearing, or toggling
+memory-mapped device registers (e.g., setting, clearing, or toggling
 bits) in the I/O space.
 \end{commentary}
 
diff --git a/src/machine.tex b/src/machine.tex
index 66c0807..47e017d 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2285,6 +2285,21 @@ reservations are yielded when any trap is taken.  In particular, any SC
 following an exception must fail, unless preceded by a suitable LR following
 that exception.
 
+Memory regions that support aligned LR/SC or aligned AMOs might also support
+misaligned LR/SC or misaligned AMOs for some addresses and access widths.  If,
+for a given address and access width, a misaligned LR/SC or AMO generates
+a misaligned address exception, then {\em all} loads, stores, LRs/SCs, and
+AMOs using that address and access width must generate misaligned address
+exceptions.
+\begin{commentary}
+Mandating that misaligned loads and stores trap wherever misaligned AMOs trap
+permits the emulation of misaligned AMOs in an M-mode trap handler.  The
+handler guarantees atomicity by acquiring a global mutex and emulating the
+access within the critical section.  Provided that the handler for misaligned
+loads and stores uses the same mutex, all accesses to a given address that
+use the same word size will be mutually atomic.
+\end{commentary}
+
 \subsection{Memory-Ordering PMAs}
 
 Regions of the address space are classified as either {\em main
diff --git a/src/preface.tex b/src/preface.tex
index f223c92..5484d52 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -47,6 +47,9 @@ The major changes in this version of the document include:
   and changed their behavior on signaling-NaN inputs to conform to the
   minimumNumber and maximumNumber operations in the proposed IEEE 754-201x
   specification.
+\item LR, SC, and AMO instructions are now permitted, but not required, to
+  support misaligned addresses, in which case regular loads and stores to
+  misaligned addresses are also atomic.
 \end{itemize}
 ~\\
 
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 97a452a..f77fec3 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -15,6 +15,9 @@ architecture proposal.  Changes from version 1.10 include:
 \item Required all harts in a system to employ the same PTE-update scheme as each other.
 \item Rectified an editing error that misdescribed the mechanism by which
   {\tt mstatus}.{\em x}IE is written upon an exception.
+\item Added the constraint that if a PMA supports LR, SC, or AMOs, but traps
+  misaligned LR, SC, or AMOs, then it also must trap
+  misaligned loads and stores.
 \end{itemize}
 
 \newpage