diff options
| author | Andrew Waterman <andrew@sifive.com> | 2018-11-06 15:48:13 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-06 15:57:31 -0800 |
| commit | fd8389aef0f0950ed9a3e4cfc4de5b8b27f1572f (patch) | |
| tree | 1820de4f6c751b378a7643854c05b478ec7b4d47 /src | |
| parent | 90f66d485cb5fd9baaeab2a36a91e3f37072590e (diff) | |
| download | riscv-isa-manual-fd8389aef0f0950ed9a3e4cfc4de5b8b27f1572f.zip riscv-isa-manual-fd8389aef0f0950ed9a3e4cfc4de5b8b27f1572f.tar.gz riscv-isa-manual-fd8389aef0f0950ed9a3e4cfc4de5b8b27f1572f.tar.bz2 | |
mcycle counts cycles across the entire core, like rdcycle
Rationale is provided in the unprivileged manual (counters.tex).
Resolves #249
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 195a8a3..0341cc7 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1516,7 +1516,8 @@ to the intermediate value of the comparand: \subsection{Hardware Performance Monitor} M-mode includes a basic hardware performance-monitoring facility. The -{\tt mcycle} CSR counts the number of cycles the hart has executed. +{\tt mcycle} CSR counts the number of clock cycles executed by the +processor core on which the hart is running. The {\tt minstret} CSR counts the number of instructions the hart has retired. The {\tt mcycle} and {\tt minstret} registers have 64-bit precision on all RV32, RV64, and RV128 systems. |