Fix typos

5 files changed, 7 insertions, 7 deletions

diff --git a/src/d.tex b/src/d.tex
index 942e350..a8decfe 100644
--- a/src/d.tex
+++ b/src/d.tex
@@ -74,7 +74,7 @@ Earlier versions of this document did not define the behavior of
 feeding the results of narrower or wider operands into an operation,
 except to require that wider saves and restores would preserve the
 value of a narrower operand.  The new definition removes this
-implementation-specific behavior, while still accomodating both
+implementation-specific behavior, while still accommodating both
 non-recoded and recoded implementations of the floating-point unit.
 The new definition also helps catch software errors by propagating
 NaNs if values are used incorrectly.
diff --git a/src/f.tex b/src/f.tex
index 9098012..72cfb7d 100644
--- a/src/f.tex
+++ b/src/f.tex
@@ -561,7 +561,7 @@ of {\em rs2}'s sign bit; and for FSGNJX, the sign bit is the XOR of
 the sign bits of {\em rs1} and {\em rs2}.  Sign-injection instructions
 do not set floating-point exception flags.  Note, FSGNJ.S {\em rx, ry,
   ry} moves {\em ry} to {\em rx} (assembler pseudo-op FMV.S {\em rx,
-  ry}); FSGNJN.S {\em rx, ry, ry} moves the the negation of {\em ry} to
+  ry}); FSGNJN.S {\em rx, ry, ry} moves the negation of {\em ry} to
 {\em rx} (assembler pseudo-op FNEG.S {\em rx, ry}); and FSGNJX.S {\em rx,
   ry, ry} moves the absolute value of {\em ry} to {\em rx} (assembler
 pseudo-op FABS.S {\em rx, ry}).
@@ -707,7 +707,7 @@ The FCLASS.S instruction examines the value in floating-point register {\em
 rs1} and writes to integer register {\em rd} a 10-bit mask that indicates
 the class of the floating-point number.  The format of the mask is
 described in Table~\ref{tab:fclass}.  The corresponding bit in {\em rd} will
-be set if the the property is true and clear otherwise.  All other bits in
+be set if the property is true and clear otherwise.  All other bits in
 {\em rd} are cleared.  Note that exactly one bit in {\em rd} will be set.
 
 \vspace{-0.2in}
diff --git a/src/machine.tex b/src/machine.tex
index 2b0d83e..1c69386 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -978,7 +978,7 @@ hand, we wish to allow flexibility for larger systems.
 Value & Name & Description \\
 \hline	 
 0      & Direct   & All exceptions set {\tt pc} to BASE. \\
-1      & Vectored & Asynchronous interrups set {\tt pc} to BASE+4$\times$cause. \\
+1      & Vectored & Asynchronous interrupts set {\tt pc} to BASE+4$\times$cause. \\
 $\ge$2 & --- & {\em Reserved} \\
 \hline
 \end{tabular}
diff --git a/src/plic.tex b/src/plic.tex
index fcf366d..0b3419d 100644
--- a/src/plic.tex
+++ b/src/plic.tex
@@ -368,7 +368,7 @@ interrupt request.
 \section{PLIC Core Specification}
 
 The operation of the PLIC core can be specified as a non-deterministic
-finite-state machine with input and output messsage queues, with the
+finite-state machine with input and output message queues, with the
 following atomic actions:
 
 \begin{itemize}
diff --git a/src/v.tex b/src/v.tex
index d48c04c..1b9dd9b 100644
--- a/src/v.tex
+++ b/src/v.tex
@@ -11,9 +11,9 @@ physical vector storage capacity and datapath parallelism.
 
 \begin{commentary}
 The vector extension is based on the style of vector register
-architecture introducted by Seymour Cray in the 1970s, as opposed to
+architecture introduced by Seymour Cray in the 1970s, as opposed to
 the earlier packed SIMD approach, introduced with the Lincoln Labs
-TX-2 in 1957 and now adopted by most other commerical instruction
+TX-2 in 1957 and now adopted by most other commercial instruction
 sets.
 
 The vector instruction set contains many features developed in earlier