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| author | Andrew Waterman <andrew@sifive.com> | 2017-12-12 17:24:28 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-12-12 17:24:28 -0800 |
| commit | f1b9ca71ffd48ed15cae6df820abeded0f607a93 (patch) | |
| tree | 6c4c07a83677bdab2e3facfb5ceef1c5c703f894 /src | |
| parent | 243563bb4faec7f7b9c704d15678bf457d27b64b (diff) | |
| download | riscv-isa-manual-f1b9ca71ffd48ed15cae6df820abeded0f607a93.zip riscv-isa-manual-f1b9ca71ffd48ed15cae6df820abeded0f607a93.tar.gz riscv-isa-manual-f1b9ca71ffd48ed15cae6df820abeded0f607a93.tar.bz2 | |
Fix typo
Diffstat (limited to 'src')
| -rw-r--r-- | src/history.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/history.tex b/src/history.tex index 5c349d0..269384c 100644 --- a/src/history.tex +++ b/src/history.tex @@ -3,7 +3,7 @@ \section{History from Revision 1.0 of ISA manual} -The RISC-V ISA and instruction set manual builds up several earlier +The RISC-V ISA and instruction set manual builds upon several earlier projects. Several aspects of the supervisor-level machine and the overall format of the manual date back to the T0 (Torrent-0) vector microprocessor project at UC Berkeley and ICSI, begun in 1992. T0 was |