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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-20 12:34:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-09-20 12:34:22 -0700 |
| commit | eff624dea22dd5039636b7e84c692cccc8db5834 (patch) | |
| tree | e1c7b5562832f77ecd6811cdb55de61362104920 /src | |
| parent | 634e7b9eeed3305b9caedb3184ed7458c78125cc (diff) | |
| download | riscv-isa-manual-eff624dea22dd5039636b7e84c692cccc8db5834.zip riscv-isa-manual-eff624dea22dd5039636b7e84c692cccc8db5834.tar.gz riscv-isa-manual-eff624dea22dd5039636b7e84c692cccc8db5834.tar.bz2 | |
Describe MSIE/SSIE/USIE
Closes #105
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index efdedc9..e7afbce 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1239,6 +1239,10 @@ result in a machine-mode write to the receiving hart's MSIP bit. A hart can write its own MSIP bit using the same memory-mapped control register. +The MSIE, SSIE, and USIE fields in the {\tt mie} CSR enable M-mode software +interrupts, S-mode software interrupts, and U-mode software interrupts, +respectively. + \begin{commentary} We only allow a hart to directly write its own SSIP or USIP bits when running in the appropriate mode, as other harts might be |