Clarify that FP loads/stores don't mutate NaN payloads

3 files changed, 9 insertions, 0 deletions

diff --git a/src/d.tex b/src/d.tex
index 022ce7d..c658ab3 100644
--- a/src/d.tex
+++ b/src/d.tex
@@ -148,6 +148,9 @@ offset[11:5] & src & base & D & offset[4:0] & STORE-FP \\
 FLD and FSD are only guaranteed to execute atomically if the effective address
 is naturally aligned and XLEN$\geq$64.
 
+FLD and FSD do not modify the bits being transferred; in particular, the
+payloads of non-canonical NaNs are preserved.
+
 \section{Double-Precision Floating-Point Computational Instructions}
 
 The double-precision floating-point computational instructions are
diff --git a/src/f.tex b/src/f.tex
index 4462164..0f54cc0 100644
--- a/src/f.tex
+++ b/src/f.tex
@@ -363,6 +363,9 @@ offset[11:5] & src & base & W & offset[4:0] & STORE-FP \\
 FLW and FSW are only guaranteed to execute atomically if the effective address
 is naturally aligned.
 
+FLW and FSW do not modify the bits being transferred; in particular, the
+payloads of non-canonical NaNs are preserved.
+
 \section{Single-Precision Floating-Point Computational Instructions}
 \label{sec:single-float-compute}
 
diff --git a/src/q.tex b/src/q.tex
index e581920..44ab317 100644
--- a/src/q.tex
+++ b/src/q.tex
@@ -64,6 +64,9 @@ offset[11:5] & src & base & Q & offset[4:0] & STORE-FP \\
 FLQ and FSQ are only guaranteed to execute atomically if the effective address
 is naturally aligned and XLEN=128.
 
+FLQ and FSQ do not modify the bits being transferred; in particular, the
+payloads of non-canonical NaNs are preserved.
+
 \section{Quad-Precision Computational Instructions}
 
 A new supported format is added to the format field of most