Clarify mtval; allow platform to specify when it's written

2 files changed, 27 insertions, 15 deletions

diff --git a/src/machine.tex b/src/machine.tex
index e7afbce..0a7a14c 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1756,13 +1756,15 @@ vector table.
 
 The {\tt mtval} register is an XLEN-bit read-write register formatted as shown
 in Figure~\ref{mtvalreg}.  When a trap is taken into M-mode, {\tt mtval} is
-written with exception-specific information to assist software in handling the
-trap.  Otherwise, {\tt mtval} is never written by the implementation, though
-it may be explicitly written by software.
+either set to zero or written with exception-specific information to assist
+software in handling the trap.  Otherwise, {\tt mtval} is never written by the
+implementation, though it may be explicitly written by software.  The hardware
+platform will specify which exceptions must set {\tt mtval} informatively and
+which may unconditionally set it to zero.
 
 When a hardware breakpoint is triggered, or an instruction-fetch, load, or
 store address-misaligned, access, or page-fault exception occurs, {\tt
-  mtval} is written with the faulting effective address.  On an illegal
+  mtval} is written with the faulting virtual address.  On an illegal
 instruction trap, {\tt mtval} may be written with the first XLEN or ILEN
 bits of the faulting instruction as described below.  For other exceptions,
 {\tt mtval} is set to zero, but a future standard may redefine {\tt
@@ -1801,10 +1803,12 @@ XLEN \\
 \label{mtvalreg}
 \end{figure}
 
-For instruction-fetch access faults on RISC-V systems with
-variable-length instructions, {\tt mtval} will contain a pointer to
-the portion of the instruction that caused the fault while {\tt mepc}
-will point to the beginning of the instruction.
+For misaligned loads and stores that cause access or page-fault exceptions,
+{\tt mtval} will contain the virtual address of the portion of the access that
+caused the fault.  For instruction-fetch access or page-fault exceptions on
+systems with variable-length instructions, {\tt mtval} will contain the
+virtual address of the portion of the instruction that caused the fault while
+{\tt mepc} will point to the beginning of the instruction.
 
 The {\tt mtval} register can optionally also be used to return the
 faulting instruction bits on an illegal instruction exception ({\tt
@@ -1846,6 +1850,8 @@ bits are cleared to zero.
   appropriate trap handling before runtime).
 \end{commentary}
 
+If the hardware platform specifies that no exceptions set {\tt mtval} to a
+nonzero value, then it may be hardwired to zero.  Otherwise,
 {\tt mtval} is a \warl\ register that must be able to hold all valid physical
 and virtual addresses and the value 0.  It need not be capable of holding all
 possible invalid addresses.  Implementations may convert some invalid address
diff --git a/src/supervisor.tex b/src/supervisor.tex
index ba8dad8..1032011 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -647,13 +647,15 @@ The {\tt stval} register is an XLEN-bit read-write register formatted as shown
 in Figure~\ref{stvalreg}.  When a trap is taken into S-mode, {\tt stval} is
 written with exception-specific information to assist software in handling the
 trap.  Otherwise, {\tt stval} is never written by the implementation, though
-it may be explicitly written by software.
+it may be explicitly written by software.  The hardware platform will specify
+which exceptions must set {\tt stval} informatively and which may
+unconditionally set it to zero.
 
 
 When a hardware breakpoint is triggered, or an instruction-fetch, load, or
 store address-misaligned, access, or page-fault exception occurs, {\tt stval}
-is written with the faulting address.  On an illegal instruction trap, {\tt
-stval} may be written with the first XLEN or ILEN bits of the faulting
+is written with the faulting virtual address.  On an illegal instruction trap,
+{\tt stval} may be written with the first XLEN or ILEN bits of the faulting
 instruction as described below.  For other exceptions, {\tt stval} is set to
 zero, but a future standard may redefine {\tt stval}'s setting for other
 exceptions.
@@ -675,10 +677,14 @@ XLEN \\
 \label{stvalreg}
 \end{figure}
 
-For instruction-fetch access faults and page faults on RISC-V systems with
-variable-length instructions, {\tt stval} will point to the portion
-of the instruction that caused the fault while {\tt sepc} will point
-to the beginning of the instruction.
+For misaligned loads and stores that cause access or page-fault
+exceptions, {\tt stval} will contain the virtual address of the
+portion of the access that caused the fault.  For
+instruction-fetch access or page-fault exceptions on systems
+with variable-length instructions, {\tt stval} will contain the
+virtual address of the portion of the instruction that caused
+the fault while {\tt sepc} will point to the beginning of the
+instruction.
 
 The {\tt stval} register can optionally also be used to return the
 faulting instruction bits on an illegal instruction exception ({\tt