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| author | Andrew Waterman <andrew@sifive.com> | 2017-10-11 12:51:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-10-11 12:51:54 -0700 |
| commit | e22b943f7a7826072620de9be269243e758cc58c (patch) | |
| tree | fbaf1df8ebedf7980f0596c068f0f93fddc50847 /src | |
| parent | 29d1e5da967db7b3ae2f817928dc207dcb4d859b (diff) | |
| download | riscv-isa-manual-e22b943f7a7826072620de9be269243e758cc58c.zip riscv-isa-manual-e22b943f7a7826072620de9be269243e758cc58c.tar.gz riscv-isa-manual-e22b943f7a7826072620de9be269243e758cc58c.tar.bz2 | |
Fix outdated commentary on mcounteren
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 0a7a14c..9960a4c 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1570,8 +1570,8 @@ n}}, respectively. The {\tt time} CSR is a read-only shadow of the memory-mapped {\tt mtime} register. \begin{commentary} Implementations can convert reads of the {\tt time} CSR into loads to -the memory-mapped {\tt mtime} register, or hard-wire the TM bits in -{\tt m{\em x}counteren} to 0 +the memory-mapped {\tt mtime} register, or hard-wire the TM bit in +{\tt mcounteren} to 0 and emulate this functionality in M-mode software. \end{commentary} |