Added commentary on fixed interrupt priority scheme for mip/mie.

Closed #13

1 files changed, 42 insertions, 0 deletions

diff --git a/src/machine.tex b/src/machine.tex
index d77e68f..222a92a 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1129,6 +1129,14 @@ and external interrupts (UEIP, SEIP) in {\tt mip}
 are writable through this CSR address; the remaining bits are
 read-only.
 
+\begin{commentary}
+  The machine-level interrupt registers handle a few root interrupt
+  sources which are assigned a fixed service priority for simplicity,
+  while separate external interrupt controllers can implement a more
+  complex prioritization scheme over a much larger set of interrupts
+  that are then muxed into the machine-level interrupt sources.
+\end{commentary}
+
 Restricted views of the {\tt mip} and {\tt mie} registers appear as
 the {\tt sip}/{\tt sie}, and {\tt uip}/{\tt uie} registers in 
 S-mode and U-mode respectively.  If an interrupt is delegated to
@@ -1330,6 +1338,40 @@ interrupts destined for the same privilege mode are handled in the following
 decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI.
 Synchronous exceptions are of lower priority than all interrupts.
 
+\begin{commentary}
+  The machine-level interrupt fixed-priority ordering rules were developed
+  with the following rationale.
+  
+  The platform-specific machine-level interrupt sources in bits 16 and
+  above have the highest service priority to support very fast local
+  vectored interrupts.
+  
+  Interrupts for higher privilege modes must be serviced before
+  interrupts for lower privilege modes to support pre-emption.
+
+  External interrupts are handled before internal (timer/software)
+  interrupts as external interrupts are usually generated by devices
+  that might require low interrupt service times.
+
+  Software interrupts are handled before internal timer interrupts,
+  because internal timer interrupts are usually intended for time
+  slicing, where time precision is less important, whereas software
+  interrupts are used for inter-processor messaging.  Software
+  interrupts can be avoided when high-precision timing is required, or
+  high-precision timer interrupts can be routed via a different
+  interrupt path.
+
+  Synchronous exceptions are given the lowest priority to minimize
+  worst-case interrupt latency.
+
+   Generally, the interrupt priority follows the bit numbering in the
+  {\tt mip} register, with higher bit numbers having higher priority,
+  but despite having higher priority than internal timer interrupts,
+  software interrupts are located in the lowest four bits of {\tt mip}
+  as these are often written by software, and this position allows the
+  use of a single CSR instruction with a five-bit immediate.
+\end{commentary}
+
 \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})}
 
 Platforms provide a real-time counter, exposed as a memory-mapped