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| author | Andrew Waterman <andrew@sifive.com> | 2020-06-10 18:26:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-06-10 18:27:18 -0700 |
| commit | d08e29e238c9cff1e4ef63389e1f1e00bff333ad (patch) | |
| tree | 8fc20ae97e5e8c830c8ff24e181ab9fb0bd276fa /src | |
| parent | 9ff515cd6695ac392e5ca32b73a135aa197e2778 (diff) | |
| download | riscv-isa-manual-d08e29e238c9cff1e4ef63389e1f1e00bff333ad.zip riscv-isa-manual-d08e29e238c9cff1e4ef63389e1f1e00bff333ad.tar.gz riscv-isa-manual-d08e29e238c9cff1e4ef63389e1f1e00bff333ad.tar.bz2 | |
Fix preface
Diffstat (limited to 'src')
| -rw-r--r-- | src/priv-preface.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index e18d9d3..879a787 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -41,8 +41,6 @@ portability problems in practice: annotations did not apply. \item Constrained the LR/SC reservation set size and shape when using page-based virtual memory. -\item PMP reset values are now platform-defined. -\item An additional 48 optional PMP registers have been defined. \end{itemize} Additionally, the following compatible changes have been made since version @@ -58,6 +56,8 @@ Additionally, the following compatible changes have been made since version \item Made priority of load/store/AMO address-misaligned exceptions implementation-defined relative to load/store/AMO page-fault and access-fault exceptions. +\item PMP reset values are now platform-defined. +\item An additional 48 optional PMP registers have been defined. \end{itemize} Finally, the hypervisor architecture proposal has been extensively revised. |