Clarify [s/m][epc/tval/cause] are only written on exceptions into that mode

2 files changed, 41 insertions, 17 deletions

diff --git a/src/machine.tex b/src/machine.tex
index d3c73f2..29938b9 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1605,8 +1605,10 @@ The {\tt mepc} register can never hold a PC value that would cause an
 instruction-address-misaligned exception.
 \end{commentary}
 
-When a trap is taken, {\tt mepc} is written with the virtual address
-of the instruction that encountered the exception.
+When a trap is taken into M-mode, {\tt mepc} is written with the virtual
+address of the instruction that encountered the exception.  Otherwise,
+{\tt mepc} is never written by the implementation, though it may be
+explicitly written by software.
 
 \begin{figure}[h!]
 {\footnotesize
@@ -1627,14 +1629,20 @@ XLEN \\
 
 \subsection{Machine Cause Register ({\tt mcause})}
 
-The {\tt mcause} register is an XLEN-bit read-write register formatted
-as shown in Figure~\ref{mcausereg}. The Interrupt bit is set if the
+The {\tt mcause} register is an XLEN-bit read-write register formatted as
+shown in Figure~\ref{mcausereg}.  When a trap is taken into M-mode, {\tt
+mcause} is written with a code indicating the event that caused the trap.
+Otherwise, {\tt mcause} is never written by the implementation, though it may be
+explicitly written by software.
+
+The Interrupt bit in the {\tt mcause} register is set if the
 trap was caused by an interrupt. The Exception Code field
  contains a code identifying the last exception.  Table~\ref{mcauses}
 lists the possible machine-level exception codes.  The Exception Code
 is an \wlrl\ field, so is only guaranteed to hold supported exception
 codes.
 
+
 \begin{figure*}[h!]
 {\footnotesize
 \begin{center}
@@ -1717,8 +1725,13 @@ vector table.
 
 \subsection{Machine Bad Bits ({\tt mtval}) Register}
 
-The {\tt mtval} register is an XLEN-bit read-write register
-formatted as shown in Figure~\ref{mtvalreg}. When a hardware
+The {\tt mtval} register is an XLEN-bit read-write register formatted as shown
+in Figure~\ref{mtvalreg}.  When a trap is taken into M-mode, {\tt mtval} is
+written with exception-specific information to assist software in handling the
+trap.  Otherwise, {\tt mtval} is never written by the implementation, though
+it may be explicitly written by software.
+
+When a hardware
 breakpoint is triggered, or an instruction-fetch, load, or store
 address-misaligned, access, or page-fault exception occurs, {\tt mtval} is
 written with the faulting effective address.  On an illegal instruction trap,
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 7872086..1b32acd 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -466,8 +466,10 @@ always zero.  On implementations that do not support instruction-set
 extensions with 16-bit instruction alignment, the two low bits ({\tt
   sepc[1:0]}) are always zero.
 
-When a trap is taken, {\tt sepc} is written with
-the virtual address of the instruction that encountered the exception.
+When a trap is taken into S-mode, {\tt sepc} is written with the virtual
+address of the instruction that encountered the exception.  Otherwise,
+{\tt sepc} is never written by the implementation, though it may be
+explicitly written by software.
 
 \begin{figure}[h!]
 {\footnotesize
@@ -488,9 +490,13 @@ XLEN \\
 
 \subsection{Supervisor Cause Register ({\tt scause})}
 
-The {\tt scause} register is an XLEN-bit read-write register formatted
-as shown in Figure~\ref{scausereg}. The Interrupt bit is set if the
-exception was caused by an interrupt. The Exception Code field
+The {\tt scause} register is an XLEN-bit read-write register formatted as
+shown in Figure~\ref{scausereg}.  When a trap is taken into S-mode, {\tt
+scause} is written with a code indicating the event that caused the trap.
+Otherwise, {\tt scause} is never written by the implementation, though it may be
+explicitly written by software.
+
+The Interrupt bit in the {\tt scause} register is set if the
 contains a code identifying the last exception.  Table~\ref{scauses}
 lists the possible exception codes for the current supervisor ISAs, in
 descending order of priority.  The Exception Code is an \wlrl\ field,
@@ -553,10 +559,15 @@ so is only guaranteed to hold supported exception codes.
 \label{scauses}
 \end{table*}
 
-\subsection{Supervisor Bad Address ({\tt sbadbits}) Register}
+\subsection{Supervisor Bad Address ({\tt stval}) Register}
+
+The {\tt stval} register is an XLEN-bit read-write register formatted as shown
+in Figure~\ref{stvalreg}.  When a trap is taken into S-mode, {\tt stval} is
+written with exception-specific information to assist software in handling the
+trap.  Otherwise, {\tt stval} is never written by the implementation, though
+it may be explicitly written by software.
 
-{\tt sbadbits} is an XLEN-bit read/write register formatted as shown in
-Figure~\ref{badvaddrreg}.  When a hardware breakpoint is triggered, or
+When a hardware breakpoint is triggered, or
 an instruction-fetch, load, or store access or page-fault exception occurs,
 or an instruction-fetch or AMO address-misaligned exception occurs,
 {\tt sbadbits} is written with the faulting address.  {\tt sbadbits}
@@ -568,7 +579,7 @@ is not modified for other exceptions.
 \begin{tabular}{@{}J}
 \instbitrange{XLEN-1}{0} \\
 \hline
-\multicolumn{1}{|c|}{\tt sbadbits} \\
+\multicolumn{1}{|c|}{\tt stval} \\
 \hline
 XLEN \\
 \end{tabular}
@@ -576,11 +587,11 @@ XLEN \\
 }
 \vspace{-0.1in}
 \caption{Supervisor bad address register.}
-\label{badvaddrreg}
+\label{stvalreg}
 \end{figure}
 
 For instruction-fetch access faults and page faults on RISC-V systems with
-variable-length instructions, {\tt sbadbits} will point to the portion
+variable-length instructions, {\tt stval} will point to the portion
 of the instruction that caused the fault while {\tt sepc} will point
 to the beginning of the instruction.