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author | Andrew Waterman <andrew@sifive.com> | 2018-08-12 16:50:12 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-08-12 16:51:09 -0700 |
commit | b8bb0553a59da2f884605736d6a249af0e45ae1f (patch) | |
tree | d846a7fb1859c7da8c8c4b8478359f6a82c6f6b0 /src | |
parent | a18153d6f4c82e895fff7978d283aa2b231eb5e4 (diff) | |
download | riscv-isa-manual-b8bb0553a59da2f884605736d6a249af0e45ae1f.zip riscv-isa-manual-b8bb0553a59da2f884605736d6a249af0e45ae1f.tar.gz riscv-isa-manual-b8bb0553a59da2f884605736d6a249af0e45ae1f.tar.bz2 |
Tweaks to M extension chapter
Diffstat (limited to 'src')
-rw-r--r-- | src/m.tex | 16 |
1 files changed, 8 insertions, 8 deletions
@@ -58,12 +58,12 @@ most-significant word of the multiplier (which contains the sign bit) with the less-significant words of the multiplicand (which are unsigned). \end{commentary} -MULW is an RV64I instruction, and multiplies the lower -32 bits of the source registers, placing the sign-extension of the -lower 32 bits of the result into the destination register. MUL can be -used to obtain the upper 32 bits of the 64-bit product, but signed -arguments must be proper 32-bit signed values, whereas unsigned -arguments must have their upper 32 bits clear. +MULW is an RV64 instruction that multiplies the lower 32 bits of the source +registers, placing the sign-extension of the lower 32 bits of the result +into the destination register. In RV64, MUL can be used to obtain the upper +32 bits of the 64-bit product, but signed arguments must be proper 32-bit +signed values, whereas unsigned arguments must have their upper 32 bits +clear. \section{Division Operations} @@ -101,11 +101,11 @@ cannot be the same as {\em rs1} or {\em rs2}). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides. -DIVW and DIVUW instructions are RV64I instructions, and divide the +DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of {\em rs1} by the lower 32 bits of {\em rs2}, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in {\em rd}, sign-extended to 64 bits. REMW and REMUW -instructions are only valid for RV64, and provide the corresponding +are RV64 instructions that provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero. |