Incorporate Allen's feedback

4 files changed, 23 insertions, 8 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 3a8ff5a..d92aa58 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2071,9 +2071,9 @@ external hard reset, brownout detected, watchdog timer elapse,
 sleep-mode wakeup), which machine-mode software and debuggers may wish
 to distinguish.
 
-{\tt mcause} reset values may alias {\tt mcause} values following
-synchronous exceptions.  There is no ambiguity in this overlap, since
-on reset the {\tt pc} is set to a different value than on other traps.
+{\tt mcause} reset values may alias {\tt mcause} values following synchronous
+exceptions.  There should be no ambiguity in this overlap, since on reset the
+{\tt pc} should be set to a different value than on other traps.
 \end{commentary}
 
 \section{Non-Maskable Interrupts}
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index da970cd..1fcab3e 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -1,5 +1,18 @@
 \chapter{Preface}
 
+This is {\bf a draft of} version 1.11 of the RISC-V privileged
+architecture proposal.  Changes from version 1.10 include:
+
+\begin{itemize}
+  \parskip 0pt
+  \itemsep 1pt
+\item Improvements to the description and commentary.
+\end{itemize}
+
+\newpage
+
+\section*{Preface to Version 1.10}
+
 This is version 1.10 of the RISC-V privileged
 architecture proposal.  Changes from version 1.9.1 include:
 
diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex
index 41ffdc6..5f50a15 100644
--- a/src/riscv-privileged.tex
+++ b/src/riscv-privileged.tex
@@ -6,7 +6,7 @@
 
 \input{preamble}
 
-\newcommand{\privrev}{1.10}
+\newcommand{\privrev}{1.11-draft}
 
 \begin{document}
 
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 26073cc..dfcfa85 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -281,8 +281,9 @@ requiring up to $4\times$XLEN-byte alignment.
 \begin{commentary}
 When vectored interrupts are enabled, interrupt cause 0, which corresponds to
 user-mode software interrupts, are vectored to the same location as
-synchronous exceptions.  This ambiguity does not arise in practice, since
-user-mode software interrupts are either disabled or delegated to user mode.
+synchronous exceptions.  This ambiguity does not arise in practice for
+supervisor software, since user-mode software interrupts are either disabled
+or delegated to user mode.
 \end{commentary}
 
 \subsection{Supervisor Interrupt Registers ({\tt sip} and {\tt sie})}
@@ -561,6 +562,7 @@ Otherwise, {\tt scause} is never written by the implementation, though it may be
 explicitly written by software.
 
 The Interrupt bit in the {\tt scause} register is set if the
+trap was caused by an interrupt. The Exception Code field
 contains a code identifying the last exception.  Table~\ref{scauses}
 lists the possible exception codes for the current supervisor ISAs, in
 descending order of priority.  The Exception Code is an \wlrl\ field,
@@ -895,8 +897,8 @@ writes and the address translation hardware.
 \end{commentary}
 
 \begin{commentary}
-Note the instruction has no effect on the translations of other RISC-V
-threads, which must be notified separately.  One approach is to use 1)
+Note the instruction has no effect on the translations of other harts,
+which must be notified separately.  One approach is to use 1)
 a local data fence to ensure local writes are visible globally, then
 2) an interprocessor interrupt to the other thread, then 3) a local
 SFENCE.VMA in the interrupt handler of the remote thread, and finally