mhcounteren -> mcounteren; mucounteren -> scounteren

Resolves #10

4 files changed, 90 insertions, 19 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 0542f4b..ae1875e 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1227,7 +1227,8 @@ and thereby avoid having to actually implement the sign-extension
 circuitry.
 \end{commentary}
 
-\subsection{Machine Counter-Enable Registers ({\tt m[h|s|u]counteren})}
+\subsection{Counter-Enable Registers ({\tt [m|h|s]counteren})}
+\label{sec:mcounteren}
 
 \begin{figure*}[h!]
 {\footnotesize
@@ -1261,30 +1262,39 @@ circuitry.
 \end{center}
 }
 \vspace{-0.1in}
-\caption{Machine counter-enable registers ({\tt mhcounteren}, {\tt mscounteren}, {\tt mucounteren}).}
-\label{mhcounteren}
+\caption{Counter-enable registers ({\tt mcounteren}, {\tt hcounteren}, {\tt scounteren}).}
+\label{mcounteren}
 \end{figure*}
 
-The machine counter-enable registers, {\tt mhcounteren}, {\tt mscounteren},
-and {\tt mucounteren}, control the availability of the hardware performance
-monitoring counters to hypervisor, supervisor, and user modes, respectively.
+The counter-enable registers {\tt mcounteren}, {\tt hcounteren}, and
+{\tt scounteren} control the availability of the
+hardware performance monitoring counters to the next-lowest privileged mode.
 
-When the CY, TM, IR, or HPM{\em n} bit in the {\tt mhcounteren} register is
+When the CY, TM, IR, or HPM{\em n} bit in the {\tt mcounteren} register is
 clear, attempts to read the {\tt cycle}, {\tt time}, {\tt instret}, or
-{\tt hpmcounter{\em n}} register while executing in H-mode
+{\tt hpmcounter{\em n}} register while executing in H-mode, S-mode, or U-mode
 will cause an illegal instruction exception.
 When one of these bits is set, access to the corresponding register is
-permitted in H-mode.
-The same bit positions in the {\tt mscounteren}
+permitted in the next implemented privilege mode (H-mode if implemented,
+otherwise S-mode if implemented, otherwise U-mode).
+
+If H-mode is implemented, the same bit positions in the {\tt hcounteren}
+register analogously control access to these registers while executing
+in S-mode.  If H-mode is permitted to access a counter register and the
+corresponding bit is set in {\tt hcounteren}, then S-mode is also permitted
+to access that register.
+
+If S-mode is implemented, the same bit positions in the {\tt scounteren}
 register analogously control access to these registers while executing
-in S-mode.  The same bit positions in the {\tt mucounteren}
-register analogously control access to these registers
-while executing in U-mode.
+in U-mode.  If S-mode is permitted to access a counter register and the
+corresponding bit is set in {\tt scounteren}, then U-mode is also permitted
+to access that register.
 
-Each counter-enable register must be implemented if the corresponding
-privilege mode is implemented.  However, any of the bits may contain
+{\tt mcounteren}, {\tt hcounteren}, and {\tt scounteren} must be implemented
+if U-mode, H-mode, and S-mode are implemented, respectively.
+However, any of the bits may contain
 a hardwired value of zero, indicating reads to the corresponding counter will
-cause an exception when executing in the corresponding privilege mode.
+cause an exception when executing in a less-privileged mode.
 Hence, they are effectively \warl\ fields.
 \begin{commentary}
 The counter-enable bits support two common use cases with minimal hardware.
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index b9993d9..34499a4 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -208,6 +208,10 @@ Number    & Privilege & Name & Description \\
 \hline
 \tt 0x180 & SRW  &\tt sptbr      & Page-table base register. \\
 \hline
+\multicolumn{4}{|c|}{Supervisor Counter Setup} \\
+\hline
+\tt 0x120 & SRW  &\tt scounteren     & Supervisor counter enable. \\
+\hline
 \end{tabular}
 \end{center}
 \caption{Currently allocated RISC-V supervisor-level CSR addresses.}
@@ -240,6 +244,10 @@ Number    & Privilege & Name & Description \\
 \hline
 \tt 0x28X & TBD & TBD & TBD. \\
 \hline
+\multicolumn{4}{|c|}{Hypervisor Counter Setup} \\
+\hline
+\tt 0x220 & HRW  &\tt hcounteren     & Hypervisor counter enable. \\
+\hline
 \end{tabular}
 \end{center}
 \caption{Currently allocated RISC-V hypervisor-level CSR addresses.}
@@ -319,9 +327,7 @@ Number    & Privilege & Name & Description \\
 \hline  
 \multicolumn{4}{|c|}{Machine Counter Setup} \\
 \hline
-\tt 0x320 & MRW  &\tt mucounteren    & User-mode counter enable. \\
-\tt 0x321 & MRW  &\tt mscounteren    & Supervisor-mode counter enable. \\
-\tt 0x322 & MRW  &\tt mhcounteren    & Hypervisor-mode counter enable. \\
+\tt 0x320 & MRW  &\tt mcounteren     & Machine counter enable. \\
 \tt 0x323 & MRW  &\tt mhpmevent3     & Machine performance-monitoring event selector. \\
 \tt 0x324 & MRW  &\tt mhpmevent4     & Machine performance-monitoring event selector. \\
 & & \multicolumn{1}{c|}{\vdots} & \ \\
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index e1c86f6..16206e9 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -13,6 +13,8 @@ proposal.  Changes from version 1.9.1 include:
 \item Hardware management of page table entry Accessed and Dirty bits has
       been made optional; simpler implementations may trap to software to
       set them.
+\item The counter-enable scheme has changed, so that H-mode and S-mode can
+      control availability of counters to S-mode and U-mode, respectively.
 \end{itemize}
 
 \section*{Preface to Version 1.9.1}
diff --git a/src/supervisor.tex b/src/supervisor.tex
index cfd42f9..418e310 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -300,6 +300,59 @@ counter values.
 The SBI must provide a facility for scheduling timer interrupts in terms
 of the real-time counter, {\tt time}.
 
+\subsection{Counter-Enable Register ({\tt scounteren})}
+
+\begin{figure*}[h!]
+{\footnotesize
+\begin{center}
+\setlength{\tabcolsep}{4pt}
+\begin{tabular}{cccMcccccc}
+\instbit{31} &
+\instbit{30} &
+\instbit{29} &
+\instbitrange{28}{6} &
+\instbit{5} &
+\instbit{4} &
+\instbit{3} &
+\instbit{2} &
+\instbit{1} &
+\instbit{0} \\
+\hline
+\multicolumn{1}{|c|}{HPM31} &
+\multicolumn{1}{c|}{HPM30} &
+\multicolumn{1}{c|}{HPM29} &
+\multicolumn{1}{c|}{...} &
+\multicolumn{1}{c|}{HPM5} &
+\multicolumn{1}{c|}{HPM4} &
+\multicolumn{1}{c|}{HPM3} &
+\multicolumn{1}{c|}{IR} &
+\multicolumn{1}{c|}{TM} &
+\multicolumn{1}{c|}{CY} \\
+\hline
+1 & 1 & 1 & 23 & 1 & 1 & 1 & 1 & 1 & 1 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{Counter-enable register ({\tt scounteren}).}
+\label{scounteren}
+\end{figure*}
+
+The counter-enable register {\tt scounteren} controls
+the availability of the
+hardware performance monitoring counters to U-mode.
+
+When the CY, TM, IR, or HPM{\em n} bit in the {\tt scounteren} register is
+clear, attempts to read the {\tt cycle}, {\tt time}, {\tt instret}, or
+{\tt hpmcounter{\em n}} register while executing in U-mode
+will cause an illegal instruction exception.  When one of these bits is set,
+access to the corresponding register is permitted.
+
+{\tt scounteren} must be implemented.  However, any of the bits may contain
+a hardwired value of zero, indicating reads to the corresponding counter will
+cause an exception when executing in U-mode.
+Hence, they are effectively \warl\ fields.
+
 \subsection{Supervisor Scratch Register ({\tt sscratch})}
 
 The {\tt sscratch} register is an XLEN-bit read/write register,