Forgot to add note to preface.

1 files changed, 5 insertions, 3 deletions

diff --git a/src/preface.tex b/src/preface.tex
index 81dfc24..755745b 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -46,10 +46,12 @@ The major changes in this version of the document include:
   Creative Commons Attribution 4.0 International Licence by the
   original authors, and this and future versions of this document will
   be released under the same licence.
+\item Rearranged chapters to put all extensions first in canonical order.
 \item Improvements to the description and commentary.
 \item Modified implicit hinting suggestion on JALR to support more efficient
   macro-op fusion of LUI/JALR and AUIPC/JALR pairs.
 \item Clarification of constraints on load-reserved/store-conditional sequences.
+\item A new table of control and status register (CSR) mappings.
 \item Clarified purpose and behavior of high-order bits of {\tt fcsr}.
 \item Corrected the description of the FNMADD.{\em fmt} and FNMSUB.{\em fmt}
       instructions, which had suggested the incorrect sign of a zero result.
@@ -60,12 +62,12 @@ The major changes in this version of the document include:
 \item Specified behavior of narrower ($<$FLEN) floating-point values held in
   wider {\tt f} registers using NaN-boxing model.
 \item Defined the exception behavior of FMA($\infty$, 0, qNaN).
-\item A draft proposal of the V vector instruction set extension.
-\item An expanded pseudoinstruction listing.
-\item A new table of control and status register (CSR) mappings.
 \item Added note indicating that the P extension might be reworked
   into an integer packed-SIMD proposal for fixed-point operations
   using the integer registers.
+\item A draft proposal of the V vector instruction set extension.
+\item An early draft proposal of the N user-level traps extension.
+\item An expanded pseudoinstruction listing.
 \item Removal of the calling convention chapter, which has been superseded by
       the RISC-V ELF psABI Specification~\cite{riscv-elf-psabi}.
 \end{itemize}