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| author | Andrew Waterman <andrew@sifive.com> | 2017-04-17 19:16:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-17 19:16:34 -0700 |
| commit | 8fd6ceb228d9a497cea697d4febf024a1efd4621 (patch) | |
| tree | c243d8cb14a18b1024ff2cb73feb42368dfcd358 /src | |
| parent | 10cc6f2c17fdbcacb9d647cfa418deda6bf64f3c (diff) | |
| download | riscv-isa-manual-8fd6ceb228d9a497cea697d4febf024a1efd4621.zip riscv-isa-manual-8fd6ceb228d9a497cea697d4febf024a1efd4621.tar.gz riscv-isa-manual-8fd6ceb228d9a497cea697d4febf024a1efd4621.tar.bz2 | |
mepc, sepc, mtval, and stval are WARL
Closes #49.
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 10 | ||||
| -rw-r--r-- | src/supervisor.tex | 10 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index e042f33..9be0432 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1605,6 +1605,11 @@ The {\tt mepc} register can never hold a PC value that would cause an instruction-address-misaligned exception. \end{commentary} +{\tt mepc} is a \warl\ register that must be able to hold all valid physical +and virtual addresses. It need not be capable of holding all possible invalid +addresses. Implementations may convert some invalid address patterns into +other invalid addresses prior to writing them to {\tt mepc}. + When a trap is taken into M-mode, {\tt mepc} is written with the virtual address of the instruction that encountered the exception. Otherwise, {\tt mepc} is never written by the implementation, though it may be @@ -1773,6 +1778,11 @@ XLEN \\ \label{mtvalreg} \end{figure} +{\tt mtval} is a \warl\ register that must be able to hold all valid physical +and virtual addresses. It need not be capable of holding all possible invalid +addresses. Implementations may convert some invalid address patterns into +other invalid addresses prior to writing them to {\tt mtval}. + For instruction-fetch access faults on RISC-V systems with variable-length instructions, {\tt mtval} will contain a pointer to the portion of the instruction that caused the fault while {\tt mepc} diff --git a/src/supervisor.tex b/src/supervisor.tex index 0f03772..a8e72ca 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -466,6 +466,11 @@ always zero. On implementations that do not support instruction-set extensions with 16-bit instruction alignment, the two low bits ({\tt sepc[1:0]}) are always zero. +{\tt sepc} is a \warl\ register that must be able to hold all valid physical +and virtual addresses. It need not be capable of holding all possible invalid +addresses. Implementations may convert some invalid address patterns into +other invalid addresses prior to writing them to {\tt sepc}. + When a trap is taken into S-mode, {\tt sepc} is written with the virtual address of the instruction that encountered the exception. Otherwise, {\tt sepc} is never written by the implementation, though it may be @@ -592,6 +597,11 @@ XLEN \\ \label{stvalreg} \end{figure} +{\tt stval} is a \warl\ register that must be able to hold all valid physical +and virtual addresses. It need not be capable of holding all possible invalid +addresses. Implementations may convert some invalid address patterns into +other invalid addresses prior to writing them to {\tt stval}. + For instruction-fetch access faults and page faults on RISC-V systems with variable-length instructions, {\tt stval} will point to the portion of the instruction that caused the fault while {\tt sepc} will point |