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| author | Andrew Waterman <andrew@sifive.com> | 2020-09-28 21:57:30 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-09-28 21:57:30 -0700 |
| commit | 8c04a22e02a871b82a4d459b635e17b9dab3cce2 (patch) | |
| tree | 870af60050edb648c775be5a3eb1de690ec95fcd /src | |
| parent | 7391e74010fc653ba1f816d40870bdb5d7049748 (diff) | |
| download | riscv-isa-manual-8c04a22e02a871b82a4d459b635e17b9dab3cce2.zip riscv-isa-manual-8c04a22e02a871b82a4d459b635e17b9dab3cce2.tar.gz riscv-isa-manual-8c04a22e02a871b82a4d459b635e17b9dab3cce2.tar.bz2 | |
Clarify that "exception code" is used for both exceptions and interrupts
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/supervisor.tex | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 62dd866..aa7b8e4 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2052,7 +2052,7 @@ explicitly written by software. The Interrupt bit in the {\tt mcause} register is set if the trap was caused by an interrupt. The Exception Code field - contains a code identifying the last exception. Table~\ref{mcauses} + contains a code identifying the last exception or interrupt. Table~\ref{mcauses} lists the possible machine-level exception codes. The Exception Code is a \wlrl\ field, so is only guaranteed to hold supported exception codes. diff --git a/src/supervisor.tex b/src/supervisor.tex index 45c1c38..53f2a3e 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -648,7 +648,7 @@ explicitly written by software. The Interrupt bit in the {\tt scause} register is set if the trap was caused by an interrupt. The Exception Code field -contains a code identifying the last exception. Table~\ref{scauses} +contains a code identifying the last exception or interrupt. Table~\ref{scauses} lists the possible exception codes for the current supervisor ISAs. The Exception Code is a \wlrl\ field. It is required to hold the values 0--31 (i.e., bits 4--0 must be implemented), but otherwise |