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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:23:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:25:49 -0700 |
| commit | 7f0b39ad953e4023af587def0b21363ebfa5759a (patch) | |
| tree | b66aeef709bd14f4eddac70fd7084151d8ae3004 /src | |
| parent | 86802858af4f070046fa4c6b530dbaa04c1da254 (diff) | |
| download | riscv-isa-manual-7f0b39ad953e4023af587def0b21363ebfa5759a.zip riscv-isa-manual-7f0b39ad953e4023af587def0b21363ebfa5759a.tar.gz riscv-isa-manual-7f0b39ad953e4023af587def0b21363ebfa5759a.tar.bz2 | |
unused mip fields are wpri instead of wiri
Diffstat (limited to 'src')
| -rw-r--r-- | src/hypervisor.tex | 10 | ||||
| -rw-r--r-- | src/machine.tex | 8 | ||||
| -rw-r--r-- | src/priv-preface.tex | 1 | ||||
| -rw-r--r-- | src/supervisor.tex | 6 |
4 files changed, 13 insertions, 12 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index d4a8c22..91e959f 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -370,13 +370,13 @@ other fields in {\tt sip} are unchanged. \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{\wiri} & +\multicolumn{1}{|c|}{\wpri} & \multicolumn{1}{c|}{SEIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{STIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SSIP} & -\multicolumn{1}{c|}{\wiri} \\ +\multicolumn{1}{c|}{\wpri} \\ \hline HSXLEN-10 & 1 & 3 & 1 & 3 & 1 & 1 \\ \end{tabular} @@ -414,7 +414,7 @@ other fields in {\tt sie} are unchanged. \multicolumn{1}{c|}{STIE} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SSIE} & -\multicolumn{1}{c|}{\wiri} \\ +\multicolumn{1}{c|}{\wpri} \\ \hline HSXLEN-10 & 1 & 3 & 1 & 3 & 1 & 1 \\ \end{tabular} diff --git a/src/machine.tex b/src/machine.tex index 3012627..199b52c 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1211,17 +1211,17 @@ to zero. \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{\wiri} & +\multicolumn{1}{|c|}{\wpri} & \multicolumn{1}{c|}{MEIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SEIP} & \multicolumn{1}{c|}{UEIP} & \multicolumn{1}{c|}{MTIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{STIP} & \multicolumn{1}{c|}{UTIP} & \multicolumn{1}{c|}{MSIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SSIP} & \multicolumn{1}{c|}{USIP} \\ \hline diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 79a2844..99862be 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -14,6 +14,7 @@ architecture proposal. Changes from version 1.10 include: \item The virtual-memory system no longer permits supervisor mode to execute instructions from user pages, regardless of the SUM setting. \item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl. +\item Made the unused {\em x}{\tt ip} fields \wpri, rather than \wiri. \item Made the unused {\tt misa} fields \wlrl, rather than \wiri. \item Required all harts in a system to employ the same PTE-update scheme as each other. \item Rectified an editing error that misdescribed the mechanism by which diff --git a/src/supervisor.tex b/src/supervisor.tex index c7d2fe1..063ee6d 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -328,13 +328,13 @@ SXLEN-bit read/write register containing interrupt enable bits. \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{\wiri} & +\multicolumn{1}{|c|}{\wpri} & \multicolumn{1}{c|}{SEIP} & \multicolumn{1}{c|}{UEIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{STIP} & \multicolumn{1}{c|}{UTIP} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SSIP} & \multicolumn{1}{c|}{USIP} \\ \hline |