Removed explicit convention on shadow CSRs.

3 files changed, 29 insertions, 20 deletions

diff --git a/src/plic.tex b/src/plic.tex
index 3319506..fcf366d 100644
--- a/src/plic.tex
+++ b/src/plic.tex
@@ -99,7 +99,7 @@ support delegating external interrupts to lower-privilege modes, then
 the lower-privilege hart contexts will not be interrupt targets.
 Interrupt notifications generated by the PLIC appear in the {\tt
   meip}/{\tt seip}/{\tt ueip} bits of the {\tt mip}/{\tt sip}/{\tt
-  uip} registers for M/H/S/U modes respectively.  The notifications
+  uip} registers for M/S/U modes respectively.  The notifications
 only appear in lower-privilege {\em x}{\tt ip} registers if external
 interrupts have been delegated to the lower-privilege modes.
 
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index 48b7ac2..fe0bce2 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -59,8 +59,8 @@ less-privileged software.
 \tt   00   &\tt   01  &\tt   XX     & \tt 0x100-0x1FF & Standard read/write \\ 
 \tt   01   &\tt   01  &\tt   00-10  & \tt 0x500-0x5BF & Standard read/write \\ 
 \tt   01   &\tt   01  &\tt   11     & \tt 0x5C0-0x5FF & Non-standard read/write \\ 
-\tt   10   &\tt   01  &\tt   00-10  & \tt 0x900-0x9BF & Standard read/write shadows \\ 
-\tt   10   &\tt   01  &\tt   11     & \tt 0x9C0-0x9FF & Non-standard read/write shadows \\ 
+\tt   10   &\tt   01  &\tt   00-10  & \tt 0x900-0x9BF & Standard read/write \\ 
+\tt   10   &\tt   01  &\tt   11     & \tt 0x9C0-0x9FF & Non-standard read/write \\ 
 \tt   11   &\tt   01  &\tt   00-10  & \tt 0xD00-0xDBF & Standard read-only \\
 \tt   11   &\tt   01  &\tt   11     & \tt 0xDC0-0xDFF & Non-standard read-only \\
 \hline
@@ -72,8 +72,8 @@ less-privileged software.
 %% \tt   00   &\tt   10  &\tt   XX     & \tt 0x200-0x2FF & Standard read/write \\ 
 %% \tt   01   &\tt   10  &\tt   00-10  & \tt 0x600-0x6BF & Standard read/write \\ 
 %% \tt   01   &\tt   10  &\tt   11     & \tt 0x6C0-0x6FF & Non-standard read/write \\ 
-%% \tt   10   &\tt   10  &\tt   00-10  & \tt 0xA00-0xABF & Standard read/write shadows \\ 
-%% \tt   10   &\tt   10  &\tt   11     & \tt 0xAC0-0xAFF & Non-standard read/write shadows \\ 
+%% \tt   10   &\tt   10  &\tt   00-10  & \tt 0xA00-0xABF & Standard read/write \\ 
+%% \tt   10   &\tt   10  &\tt   11     & \tt 0xAC0-0xAFF & Non-standard read/write \\ 
 %% \tt   11   &\tt   10  &\tt   00-10  & \tt 0xE00-0xEBF & Standard read-only \\
 %% \tt   11   &\tt   10  &\tt   11     & \tt 0xEC0-0xEFF & Non-standard read-only \\
 \hline
@@ -84,8 +84,8 @@ less-privileged software.
 \tt   01   &\tt   11  &\tt   10     & \tt 0x7A0-0x7AF & Standard read/write debug CSRs  \\ 
 \tt   01   &\tt   11  &\tt   10     & \tt 0x7B0-0x7BF & Debug-mode-only CSRs \\
 \tt   01   &\tt   11  &\tt   11     & \tt 0x7C0-0x7FF & Non-standard read/write \\ 
-\tt   10   &\tt   11  &\tt   00-10  & \tt 0xB00-0xBBF & Standard read/write shadows \\ 
-\tt   10   &\tt   11  &\tt   11     & \tt 0xBC0-0xBFF & Non-standard read/write shadows \\ 
+\tt   10   &\tt   11  &\tt   00-10  & \tt 0xB00-0xBBF & Standard read/write \\ 
+\tt   10   &\tt   11  &\tt   11     & \tt 0xBC0-0xBFF & Non-standard read/write \\ 
 \tt   11   &\tt   11  &\tt   00-10  & \tt 0xF00-0xFBF & Standard read-only \\
 \tt   11   &\tt   11  &\tt   11     & \tt 0xFC0-0xFFF & Non-standard read-only \\
 \hline
@@ -104,14 +104,20 @@ are read-only, in which case writes to the read-only bits are ignored.
 Table~\ref{csrrwpriv} also indicates the convention to allocate CSR
 addresses between standard and non-standard uses.  The CSR addresses
 reserved for non-standard uses will not be redefined by future
-standard extensions.  The shadow addresses are reserved to provide a
-read-write address via which a higher privilege level can modify a
-register that is read-only at a lower privilege level.  Note that if
-one privilege level has already allocated a read/write shadow
-address, then any higher privilege level can use the same CSR address
-for read/write access to the same register.
+standard extensions.
 
 \begin{commentary}
+We have dropped the explicit allocation of CSR space for shadow CSRs
+to leave more flexibility for allocated other CSRs. Shadow CSRs can
+still be added in the appropriate R/W space.  The counters are the
+only shadowed CSRs in the current spec.
+
+Shadows CSRs provide a read-write address via which a higher privilege
+level can modify a register that is read-only at a lower privilege
+level.  Note that if one privilege level has already allocated a
+read/write shadow address, then any higher privilege level can use the
+same CSR address for read/write access to the same register.
+  
 Effective virtualization requires that as many instructions run
 natively as possible inside a virtualized environment, while any
 privileged accesses trap to the virtual machine
@@ -130,10 +136,11 @@ illegal instruction exceptions on machine-mode access to these registers.
 
 Tables~\ref{ucsrnames}--\ref{mcsrnames} list the CSRs that have
 currently been allocated CSR addresses.  The timers, counters, and
-floating-point CSRs are the only standard user-level CSRs currently
-defined.  The other registers are used by privileged code, as described
-in the following chapters.  Note that not all registers are required
-on all implementations.
+floating-point CSRs are standard user-level CSRs, as well as the
+additional user trap registers added by the N extension.  The other
+registers are used by privileged code, as described in the following
+chapters.  Note that not all registers are required on all
+implementations.
 
 \begin{table}[htb!]
 \begin{center}
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 437b21e..0cee249 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -10,6 +10,8 @@ architecture proposal.  Changes from version 1.9.1 include:
   Creative Commons Attribution 4.0 International Licence by the
   original authors, and this and future versions of this document will
   be released under the same licence.
+\item The explicit convention on shadow CSR addresses has been removed to
+  reclaim CSR space.  Shadow CSRs can still be added as needed.
 \item The interrupt-enable stack discipline has been simplified.
 \item An optional mechanism to change the base ISA used by supervisor
   and user modes has been added, and the field previously called Base
@@ -18,6 +20,9 @@ architecture proposal.  Changes from version 1.9.1 include:
   {\tt mstatus} register to the {\tt sptbr} register.
 \item The SFENCE.VM instruction has been removed in favor of the improved
   SFENCE.VMA instruction.
+\item The {\tt mstatus} bit MXR has been exposed to S-mode via {\tt sstatus}.
+\item The polarity of the PUM bit in {\tt sstatus} has been inverted to
+  shorten code sequences involving MXR.  The bit has been renamed to SUM.
 \item Hardware management of page-table entry Accessed and Dirty bits has
   been made optional; simpler implementations may trap to software to
   set them.
@@ -28,9 +33,6 @@ architecture proposal.  Changes from version 1.9.1 include:
   reserved and may be repurposed at a later date.
 \item A mechanism to improve virtualization performance by
   trapping S-mode virtual-memory management operations has been added.
-\item The {\tt mstatus} bit MXR has been exposed to S-mode via {\tt sstatus}.
-\item The polarity of the PUM bit in {\tt sstatus} has been inverted to
-  shorten code sequences involving MXR.  The bit has been renamed to SUM.
 \end{itemize}
 
 \newpage