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| author | Andrew Waterman <aswaterman@gmail.com> | 2018-10-04 15:06:29 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-04 15:06:29 -0700 |
| commit | 71597dd3ad89a2262d240680793586a8ebdec308 (patch) | |
| tree | 3109940a0dbc70f560338fb6caab15d512395f1e /src | |
| parent | 4abbead1038fa9366b177d289ebcf0b8da503617 (diff) | |
| download | riscv-isa-manual-71597dd3ad89a2262d240680793586a8ebdec308.zip riscv-isa-manual-71597dd3ad89a2262d240680793586a8ebdec308.tar.gz riscv-isa-manual-71597dd3ad89a2262d240680793586a8ebdec308.tar.bz2 | |
Add marchid management document (#234)
* Fix broken link
* Add marchid document
Diffstat (limited to 'src')
| -rw-r--r-- | src/rv32.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 60723b6..0aab4f5 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -202,7 +202,7 @@ U-type \\ The RISC-V ISA keeps the source ({\em rs1} and {\em rs2}) and destination ({\em rd}) registers at the same position in all formats to simplify decoding. Except for the 5-bit immediates used in CSR -instructions (Section~\ref{sec:csrinsts}), immediates are always +instructions (Chapter~\ref{csrinsts}), immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity. In particular, the sign bit for all immediates is always |