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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2019-08-27 19:12:04 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2019-08-27 19:12:04 -0700 |
| commit | 66d31a74b98816dd756a0e00e3c208c51e18ddee (patch) | |
| tree | 7b53be5aadeaa03a73596cacd6b2cb0800263a8e /src | |
| parent | 66307de8aee6a8b8a7021e1e9476b78dedf61390 (diff) | |
| download | riscv-isa-manual-66d31a74b98816dd756a0e00e3c208c51e18ddee.zip riscv-isa-manual-66d31a74b98816dd756a0e00e3c208c51e18ddee.tar.gz riscv-isa-manual-66d31a74b98816dd756a0e00e3c208c51e18ddee.tar.bz2 | |
Closes #359.
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 0a13883..bb02579 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -326,7 +326,8 @@ The {\tt mhartid} CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. This register must be readable in any implementation. Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, -but at least one hart must have a hart ID of zero. Hart IDs must be unique. +but at least one hart must have a hart ID of zero. Hart IDs must be +unique within the execution environment. \begin{figure*}[h!] {\footnotesize |