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| author | Andrew Waterman <andrew@sifive.com> | 2019-08-27 14:39:50 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-08-27 14:39:50 -0700 |
| commit | 66307de8aee6a8b8a7021e1e9476b78dedf61390 (patch) | |
| tree | 3a2d2a4247d409d527548acc26d17bf7fc4af8dc /src | |
| parent | c32040f6455c070c6327badac5de579a9a540ddc (diff) | |
| download | riscv-isa-manual-66307de8aee6a8b8a7021e1e9476b78dedf61390.zip riscv-isa-manual-66307de8aee6a8b8a7021e1e9476b78dedf61390.tar.gz riscv-isa-manual-66307de8aee6a8b8a7021e1e9476b78dedf61390.tar.bz2 | |
Like page-table walks, main memory might not support i-fetch
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index bacf432..0a13883 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2604,8 +2604,16 @@ I/O devices and might therefore need to know which access sizes are supported. \end{commentary} -Main memory regions always support read, write, and execute of all -access widths required by the attached devices. +Main memory regions always support read and write of all +access widths required by the attached devices, and can +specify whether instruction fetch is supported. + +\begin{commentary} +Some platforms might mandate that all of main memory support instruction +fetch. +Other platforms might prohibit instruction fetch from some main memory +regions. +\end{commentary} \begin{commentary} In some cases, the design of a processor or device accessing main |