Reordered chapters to be somewhat more logical.

3 files changed, 7 insertions, 6 deletions

diff --git a/src/intro.tex b/src/intro.tex
index 00c3bef..3d32741 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -431,7 +431,7 @@ The base RISC-V ISA has a little-endian memory system, but
 non-standard variants can provide a big-endian or bi-endian memory
 system.  Instructions are stored in memory with each 16-bit parcel
 stored in a memory halfword according to the implementation's natural
-endianness. Parcels comprising one instruction are stored at
+endianness. Parcels forming one instruction are stored at
 increasing halfword addresses, with the lowest addressed parcel
 holding the lowest numbered bits in the instruction specification,
 i.e., instructions are always stored in a little-endian sequence of
diff --git a/src/preface.tex b/src/preface.tex
index 50832ef..940d00f 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -34,7 +34,8 @@ versions of the RISC-V ISA modules:
 
 To date, no parts of the standard have been officially ratified by the
 RISC-V Foundation, but the components labeled ``frozen'' above are not
-expected to change during the ratification process.
+expected to change during the ratification process beyond resolving
+ambiguities and holes in the specification.
 
 The major changes in this version of the document include:
 \begin{itemize}
diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex
index 970d981..c27c4f5 100644
--- a/src/riscv-spec.tex
+++ b/src/riscv-spec.tex
@@ -67,13 +67,11 @@
 \input{rv32}
 \input{rv32e}
 \input{rv64}
+\input{rv128}
 \input{m}
 \input{a}
 \input{f}
 \input{d}
-\input{gmaps}
-\input{extensions}
-\input{naming}
 \input{q}
 \input{l}
 \input{c}
@@ -82,8 +80,10 @@
 \input{j}
 \input{t}
 \input{p}
-\input{rv128}
+\input{gmaps}
 \input{assembly}
+\input{extensions}
+\input{naming}
 \input{history}
 
 \bibliographystyle{plain}