Added note indicating that the P extension might be reworked

into an integer packed-SIMD proposal for fixed-point operations
using the integer registers.

2 files changed, 12 insertions, 0 deletions

diff --git a/src/p.tex b/src/p.tex
index f66acf7..b360294 100644
--- a/src/p.tex
+++ b/src/p.tex
@@ -2,6 +2,15 @@
   Version 0.1}
 \label{sec:packedsimd}
 
+\begin{commentary}
+  Discussions at the 5th RISC-V workshop indicated a desire to drop
+  this packed-SIMD proposal for floating-point registers in favor of
+  standardizing on the V extension for large floating-point SIMD
+  operations.  However, there was interest in packed-SIMD fixed-point
+  operations for use in the integer registers of small RISC-V
+  implementations.
+\end{commentary}
+
 In this chapter, we outline a standard packed-SIMD extension for
 RISC-V.  We've reserved the instruction subset name ``P'' for a future
 standard set of packed-SIMD extensions.  Many other extensions can
diff --git a/src/preface.tex b/src/preface.tex
index 940d00f..d77007e 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -62,6 +62,9 @@ The major changes in this version of the document include:
 \item A draft proposal of the V vector instruction set extension.
 \item An expanded pseudoinstruction listing.
 \item A new table of control and status register (CSR) mappings.
+\item Added note indicating that the P extension might be reworked
+  into an integer packed-SIMD proposal for fixed-point operations
+  using the integer registers.
 \item Removal of the calling convention chapter, which has been superseded by
       the RISC-V ELF psABI Specification~\cite{riscv-elf-psabi}.
 \end{itemize}