Add TW bit

1 files changed, 24 insertions, 12 deletions

diff --git a/src/machine.tex b/src/machine.tex
index d3b19d5..739c254 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -325,28 +325,29 @@ privilege-level ISAs respectively.
 \begin{tabular}{cKcccccc}
 \\
 \instbit{31} &
-\instbitrange{30}{21} &
+\instbitrange{30}{22} &
+\instbit{21} &
 \instbit{20} &
 \instbit{19} &
 \instbit{18} &
 \instbit{17} &
-\instbitrange{16}{15} &
  \\
 \hline
 \multicolumn{1}{|c|}{SD} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{TW} &
 \multicolumn{1}{c|}{TVM} &
 \multicolumn{1}{c|}{MXR} &
 \multicolumn{1}{c|}{PUM} &
 \multicolumn{1}{c|}{MPRV} &
-\multicolumn{1}{c|}{XS[1:0]} &
  \\
 \hline
-1 & 12 & 1 & 1 & 1 & 1 & 2 & \\
+1 & 9 & 1 & 1 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{ccccccccccccc}
+\begin{tabular}{cccccccccccccc}
 \\
 &
+\instbitrange{16}{15} &
 \instbitrange{14}{13} &
 \instbitrange{12}{11} &
 \instbitrange{10}{9} &
@@ -361,6 +362,7 @@ privilege-level ISAs respectively.
 \instbit{0} \\
 \hline
  &
+\multicolumn{1}{c|}{XS[1:0]} &
 \multicolumn{1}{|c|}{FS[1:0]} &
 \multicolumn{1}{c|}{MPP[1:0]} &
 \multicolumn{1}{c|}{HPP[1:0]} &
@@ -393,12 +395,12 @@ privilege-level ISAs respectively.
 \instbitrange{XLEN-2}{36} &
 \instbitrange{35}{34} &
 \instbitrange{33}{32} &
-\instbitrange{31}{21} &
+\instbitrange{31}{20} &
+\instbit{21} &
 \instbit{20} &
 \instbit{19} &
 \instbit{18} &
 \instbit{17} &
-\instbitrange{16}{15} &
  \\
 \hline
 \multicolumn{1}{|c|}{SD} &
@@ -406,18 +408,19 @@ privilege-level ISAs respectively.
 \multicolumn{1}{c|}{SXL} &
 \multicolumn{1}{c|}{UXL} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{TW} &
 \multicolumn{1}{c|}{TVM} &
 \multicolumn{1}{c|}{MXR} &
 \multicolumn{1}{c|}{PUM} &
 \multicolumn{1}{c|}{MPRV} &
-\multicolumn{1}{c|}{XS[1:0]} &
  \\
 \hline
-1 & XLEN-37 & 2 & 2 & 11 & 1 & 1 & 1 & 1 & 2 & \\
+1 & XLEN-37 & 2 & 2 & 10 & 1 & 1 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{ccccccccccccc}
+\begin{tabular}{cccccccccccccc}
 \\
 &
+\instbitrange{16}{15} &
 \instbitrange{14}{13} &
 \instbitrange{12}{11} &
 \instbitrange{10}{9} &
@@ -432,6 +435,7 @@ privilege-level ISAs respectively.
 \instbit{0} \\
 \hline
  &
+\multicolumn{1}{c|}{XS[1:0]} &
 \multicolumn{1}{|c|}{FS[1:0]} &
 \multicolumn{1}{c|}{MPP[1:0]} &
 \multicolumn{1}{c|}{HPP[1:0]} &
@@ -445,7 +449,7 @@ privilege-level ISAs respectively.
 \multicolumn{1}{c|}{SIE} &
 \multicolumn{1}{c|}{UIE} \\
 \hline
- & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
+ & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -602,6 +606,7 @@ supervisor virtual-memory management operations.  When TVM=1,
 attempts to read or write {\tt sptbr} or execute the SFENCE.VMA
 instruction while executing in S-mode will raise an illegal instruction
 exception.  When TVM=0, these operations are permitted in S-mode.
+TVM is hard-wired to 0 when S-mode is not supported.
 
 \begin{commentary}
 The TVM mechanism improves virtualization efficiency by permitting guest
@@ -613,7 +618,14 @@ Trapping {\tt sptbr} accesses and the SFENCE.VMA instruction provides the
 hooks necessary to lazily populate shadow page tables.
 \end{commentary}
 
-\note{AW: Describe TW bit, or make WFI M-only.}
+The TW (Timeout Wait) bit supports intercepting the WFI instruction (see
+Section~\ref{wfi}).  When TW=0, the WFI instruction is permitted in S-mode.
+When TW=1, if WFI is executed in S-mode, and it does not complete within an
+implementation-specific, bounded time limit, the WFI instruction causes an
+illegal instruction trap.  The time limit may always be 0, in which case WFI
+always causes an illegal instruction trap in S-mode when TW=1.
+TW is hard-wired to 0 when S-mode is not supported.
+
 \begin{commentary}
 Trapping the WFI
 instruction can trigger a world switch to another guest OS, rather than