diff options
| author | David Horner <ds2horner@gmail.com> | 2017-03-02 10:14:52 -0500 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-06 23:50:46 -0800 |
| commit | 5727c3089d5b5b9737de5e14c5cc75d15d36a756 (patch) | |
| tree | 197c6b0e53175f45bd6af785c058a2f39830ad57 /src | |
| parent | c17a3fddbb8d0cb334669bf2925fc8fead22cf7e (diff) | |
| download | riscv-isa-manual-5727c3089d5b5b9737de5e14c5cc75d15d36a756.zip riscv-isa-manual-5727c3089d5b5b9737de5e14c5cc75d15d36a756.tar.gz riscv-isa-manual-5727c3089d5b5b9737de5e14c5cc75d15d36a756.tar.bz2 | |
One liners to correct register designation in rvc-instr-table
No initial register value is not used by C.LI, so only rd is valid.
No initial register value is not used by C.LUI, so only rd is valid.
Both r1 and rd are set by the C.ADD expansion (to the same register id)
Diffstat (limited to 'src')
| -rw-r--r-- | src/rvc-instr-table.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex index b4bc8c6..e7843eb 100644 --- a/src/rvc-instr-table.tex +++ b/src/rvc-instr-table.tex @@ -198,7 +198,7 @@ & \multicolumn{3}{|c|}{010} & \multicolumn{1}{c|}{imm[5]} & -\multicolumn{5}{c|}{rs1/rd$\neq$0} & +\multicolumn{5}{c|}{rd$\neq$0} & \multicolumn{5}{c|}{imm[4:0]} & \multicolumn{2}{c|}{01} & C.LI {\em \tiny (HINT, rd=0)} \\ \whline{2-17} @@ -214,7 +214,7 @@ & \multicolumn{3}{|c|}{011} & \multicolumn{1}{c|}{nzimm[17]} & -\multicolumn{5}{c|}{rs1/rd$\neq$$\{0,2\}$} & +\multicolumn{5}{c|}{rd$\neq$$\{0,2\}$} & \multicolumn{5}{c|}{nzimm[16:12]} & \multicolumn{2}{c|}{01} & C.LUI {\em \tiny (RES, nzimm=0; HINT, rd=0)}\\ \whline{2-17} @@ -489,7 +489,7 @@ & \multicolumn{3}{|c|}{100} & \multicolumn{1}{c|}{1} & -\multicolumn{5}{c|}{rd$\neq$0} & +\multicolumn{5}{c|}{rs1/rd$\neq$0} & \multicolumn{5}{c|}{rs2$\neq$0} & \multicolumn{2}{c|}{10} & C.ADD {\em \tiny (HINT, rd=0)} \\ \whline{2-17} |