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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-21 03:55:56 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-21 03:55:56 -0800 |
| commit | 4e6e798bcad34dc4becb5bcb3e0516200a890057 (patch) | |
| tree | f40b8c33972a8f566c2b3a590bf0d4adf1cbaa9a /src | |
| parent | 9ffebdbb329d43893d62df5af47ae1a4602a18cc (diff) | |
| download | riscv-isa-manual-4e6e798bcad34dc4becb5bcb3e0516200a890057.zip riscv-isa-manual-4e6e798bcad34dc4becb5bcb3e0516200a890057.tar.gz riscv-isa-manual-4e6e798bcad34dc4becb5bcb3e0516200a890057.tar.bz2 | |
note that xtval is written upon a trap
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index a18db60..9ab204e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1093,7 +1093,9 @@ registers should not exist. When a trap is delegated to a less-privileged mode {\em x}, the {\em x}\,{\tt cause} register is written with the trap cause; the {\em x}\,{\tt epc} register is written with the virtual address of -the instruction that took the trap; the {\em x}\,PP field +the instruction that took the trap; the +{\em x}\,{\tt tval} register is written with an +exception-specific datum; the {\em x}\,PP field of {\tt mstatus} is written with the active privilege mode at the time of the trap; the {\em x}\,PIE field of {\tt mstatus} is written with the value of the {\em x}\,IE field at the time of the trap; and |