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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-13 13:09:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-13 13:09:55 -0700 |
| commit | 4bba8d8c27f5c02af26bc926123d4a25ffe4f9d0 (patch) | |
| tree | ce8e3c6c3c0294eccef1a254db6f0c64e17a5f88 /src | |
| parent | 63ad6378a897456aa38896bd4d10b18128918114 (diff) | |
| download | riscv-isa-manual-4bba8d8c27f5c02af26bc926123d4a25ffe4f9d0.zip riscv-isa-manual-4bba8d8c27f5c02af26bc926123d4a25ffe4f9d0.tar.gz riscv-isa-manual-4bba8d8c27f5c02af26bc926123d4a25ffe4f9d0.tar.bz2 | |
C.SLLI takes both rs1 and rd args
Diffstat (limited to 'src')
| -rw-r--r-- | src/rvc-instr-table.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex index e7843eb..a990587 100644 --- a/src/rvc-instr-table.tex +++ b/src/rvc-instr-table.tex @@ -401,7 +401,7 @@ & \multicolumn{3}{|c|}{000} & \multicolumn{1}{c|}{nzimm[5]} & -\multicolumn{5}{c|}{rd$\neq$0} & +\multicolumn{5}{c|}{rs1/rd$\neq$0} & \multicolumn{5}{c|}{nzimm[4:0]} & \multicolumn{2}{c|}{10} & C.SLLI {\em \tiny (HINT, rd=0; RV32 NSE, nzimm[5]=1)} \\ \cline{2-17} @@ -409,7 +409,7 @@ & \multicolumn{3}{|c|}{000} & \multicolumn{1}{c|}{0} & -\multicolumn{5}{c|}{rd$\neq$0} & +\multicolumn{5}{c|}{rs1/rd$\neq$0} & \multicolumn{5}{c|}{0} & \multicolumn{2}{c|}{10} & C.SLLI64 {\em \tiny (RV128; RV32/64 HINT; HINT, rd=0)} \\ \whline{2-17} |