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| author | Daniel Lustig <dlustig@nvidia.com> | 2017-12-13 16:25:33 -0800 |
|---|---|---|
| committer | Daniel Lustig <dlustig@nvidia.com> | 2017-12-13 16:25:33 -0800 |
| commit | 056ec92a60c4a575f54f2f50843476cde9f36e98 (patch) | |
| tree | cffa97c190f9369ce9dd4f33a241c1f357c57bae /src | |
| parent | 4b5852c190f3eff38c471b6d5e1a5f1adc7d9142 (diff) | |
| download | riscv-isa-manual-056ec92a60c4a575f54f2f50843476cde9f36e98.zip riscv-isa-manual-056ec92a60c4a575f54f2f50843476cde9f36e98.tar.gz riscv-isa-manual-056ec92a60c4a575f54f2f50843476cde9f36e98.tar.bz2 | |
Fix typo
Diffstat (limited to 'src')
| -rw-r--r-- | src/memory.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/memory.tex b/src/memory.tex index 94e3733..dd0a1fe 100644 --- a/src/memory.tex +++ b/src/memory.tex @@ -179,7 +179,7 @@ memory access $a$ precedes memory access $b$ in preserved program order (and hen \begin{itemize} \item (a) precedes (b): by rule X \item (b) precedes (d): by rule \ref{ppo:fence} - \item (d) precedes (e): by the load value axiom. Otherwise, if (d) preceded (c), then (d) would be required to return the value 1. (This is a perfectly legal execution; it's just not the one in question) + \item (d) precedes (e): by the load value axiom. Otherwise, if (e) preceded (d), then (d) would be required to return the value 1. (This is a perfectly legal execution; it's just not the one in question) \item (e) precedes (f): by rule X \item (f) precedes (h): by rule \ref{ppo:fence} \item (h) precedes (a): by the load value axiom, as above. |