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authorAndrew Waterman <andrew@sifive.com>2019-01-18 10:46:34 -0800
committerAndrew Waterman <andrew@sifive.com>2019-01-18 10:46:34 -0800
commit0420fc341ad951340ba3b9e2372768a5421e22d5 (patch)
tree6a189de9296ca28c9070e617ffd772dd784be702 /src
parentb6527e1b18eb0110007dc24794addccb04bebc41 (diff)
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Clarify that FMV.X.W doesn't canonicalize NaN payloads
We said this explicitly for FMV.W.X, but not the other way around.
Diffstat (limited to 'src')
-rw-r--r--src/d.tex3
-rw-r--r--src/f.tex5
2 files changed, 7 insertions, 1 deletions
diff --git a/src/d.tex b/src/d.tex
index c658ab3..097422e 100644
--- a/src/d.tex
+++ b/src/d.tex
@@ -328,6 +328,9 @@ representation in IEEE 754-2008 standard encoding in integer register
754-2008 standard encoding from the integer register {\em rs1} to the
floating-point register {\em rd}.
+FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the
+payloads of non-canonical NaNs are preserved.
+
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
diff --git a/src/f.tex b/src/f.tex
index 347ebfd..0f8d19c 100644
--- a/src/f.tex
+++ b/src/f.tex
@@ -647,7 +647,10 @@ Instructions are provided to move bit patterns between the
floating-point and integer registers. FMV.X.W moves the
single-precision value in floating-point register {\em rs1}
represented in IEEE 754-2008 encoding to the lower 32 bits of integer
-register {\em rd}. For RV64, the higher 32 bits of the destination
+register {\em rd}. The bits are not
+modified in the transfer, and in particular, the payloads of
+non-canonical NaNs are preserved.
+For RV64, the higher 32 bits of the destination
register are filled with copies of the floating-point number's sign
bit.