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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-30 00:15:23 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-30 00:15:23 -0700 |
| commit | f70eec9c3960205358af76dc195b605c888201e9 (patch) | |
| tree | 77b4426c69c0e318a6f2b853361a682ba5d7a576 /src | |
| parent | ddaabb00e29f0e981213a68fd681367cafc5c52e (diff) | |
| download | riscv-isa-manual-f70eec9c3960205358af76dc195b605c888201e9.zip riscv-isa-manual-f70eec9c3960205358af76dc195b605c888201e9.tar.gz riscv-isa-manual-f70eec9c3960205358af76dc195b605c888201e9.tar.bz2 | |
clarification
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 5390879..34b3b3d 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2233,7 +2233,7 @@ Most systems will require that at least some PMAs are dynamically checked in hardware later in the execution pipeline after the physical address is known, as some operations will not be supported at all physical memory addresses, and some operations require knowing the -current setting of a configurable PMA attribute. While many other systems +current setting of a configurable PMA attribute. While many other architectures specify some PMAs in the virtual memory page tables and use the TLB to inform the pipeline of these properties, this approach injects platform-specific information into a virtualized layer and can cause system errors |