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| author | Palmer Dabbelt <palmer@sifive.com> | 2018-08-01 16:23:02 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-08-01 16:27:43 -0700 |
| commit | 9d2ff967999836293e424ef697a9a065f070dc50 (patch) | |
| tree | 4fa6fb55d68c0364d883f58e7120d4f3e4f78047 /src | |
| parent | 016c5c7ece6536c07cc4982f3bdd47a697a0c586 (diff) | |
| download | riscv-isa-manual-9d2ff967999836293e424ef697a9a065f070dc50.zip riscv-isa-manual-9d2ff967999836293e424ef697a9a065f070dc50.tar.gz riscv-isa-manual-9d2ff967999836293e424ef697a9a065f070dc50.tar.bz2 | |
Un-mix trap and exception in {m,s}epctrap
This might be a bit pedantic, but the current wording in the spec mixes
up traps and execptions here in a way that makes it sound like
interrupts don't write {m,s}epc if you're reading quickly.
I don't really like the wording I've proposed, so this is more of a bug
report than a fix.
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 5 | ||||
| -rw-r--r-- | src/supervisor.tex | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index 34b3b3d..edfd53f 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1723,8 +1723,9 @@ addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt mepc}. When a trap is taken into M-mode, {\tt mepc} is written with the virtual -address of the instruction that encountered the exception. Otherwise, -{\tt mepc} is never written by the implementation, though it may be +address of the instruction that encountered the exception or the virtual +address of the next instruction to be executed in the interrupted context. +Otherwise, {\tt mepc} is never written by the implementation, though it may be explicitly written by software. \begin{figure}[h!] diff --git a/src/supervisor.tex b/src/supervisor.tex index bd432a1..5e72401 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -558,8 +558,9 @@ addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt sepc}. When a trap is taken into S-mode, {\tt sepc} is written with the virtual -address of the instruction that encountered the exception. Otherwise, -{\tt sepc} is never written by the implementation, though it may be +address of the instruction that encountered the exception or the virtual +address of the next instruction to be executed in the interrupted context. +Otherwise, {\tt sepc} is never written by the implementation, though it may be explicitly written by software. \begin{figure}[h!] |