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| author | Tynan McAuley <tymcauley@gmail.com> | 2018-06-16 22:47:14 -0400 |
|---|---|---|
| committer | Tynan McAuley <tymcauley@gmail.com> | 2018-06-16 23:17:29 -0400 |
| commit | 842be4110c382c77bdb9430d1fcdae5ad00ebe57 (patch) | |
| tree | 04d7cc9811f65d6d61b0c75c970af1984abd8dda /src | |
| parent | 584397f1c81bd01b1458fcc6dab12adc56fa19df (diff) | |
| download | riscv-isa-manual-842be4110c382c77bdb9430d1fcdae5ad00ebe57.zip riscv-isa-manual-842be4110c382c77bdb9430d1fcdae5ad00ebe57.tar.gz riscv-isa-manual-842be4110c382c77bdb9430d1fcdae5ad00ebe57.tar.bz2 | |
Fixed register name formatting error in rv32.tex.
Changed a monospace "rd" to an italics "rd". Instruction fields that are
inline with text are always formatted as italics, not monospace.
Diffstat (limited to 'src')
| -rw-r--r-- | src/rv32.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 68057e9..e079bf4 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -984,7 +984,7 @@ from memory to register {\em rd}. Stores copy the value in register The LW instruction loads a 32-bit value from memory into {\em rd}. LH loads a 16-bit value from memory, then sign-extends to 32-bits before -storing in {\tt rd}. LHU loads a 16-bit value from memory but then +storing in {\em rd}. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in {\em rd}. LB and LBU are defined analogously for 8-bit values. The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register |