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author | Tynan McAuley <tymcauley@gmail.com> | 2018-06-16 22:44:42 -0400 |
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committer | Tynan McAuley <tymcauley@gmail.com> | 2018-06-16 22:44:42 -0400 |
commit | 584397f1c81bd01b1458fcc6dab12adc56fa19df (patch) | |
tree | f456f05f2222ea3ee78521e9ea2e544167d4fb8d /src | |
parent | 6729ff0f387736d6adceb30088e2360c2ff418eb (diff) | |
download | riscv-isa-manual-584397f1c81bd01b1458fcc6dab12adc56fa19df.zip riscv-isa-manual-584397f1c81bd01b1458fcc6dab12adc56fa19df.tar.gz riscv-isa-manual-584397f1c81bd01b1458fcc6dab12adc56fa19df.tar.bz2 |
Fixed grammar inconsistency in a.tex.
Changed "can not" to "cannot". While both are acceptable, "cannot" is
used throughout the document.
Diffstat (limited to 'src')
-rw-r--r-- | src/a.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -43,7 +43,7 @@ atomic memory operation is treated as an {\em acquire} access, i.e., no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation. If only the {\em rl} bit is set, the atomic memory operation is treated as a {\em - release} access, i.e., the release memory operation can not be + release} access, i.e., the release memory operation cannot be observed to take place before any earlier memory operations on this RISC-V hart. If both the {\em aq} and {\em rl} bits are set, the atomic memory operation is {\em sequentially consistent} and cannot be |