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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-12 16:44:02 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-12 16:44:02 -0700 |
| commit | a18153d6f4c82e895fff7978d283aa2b231eb5e4 (patch) | |
| tree | db598f2e8e5944e9a33cb6c27cc05544ec64b13a /src | |
| parent | 931d0e6f4601c9e09a9af20bd2638b3df6bab26c (diff) | |
| download | riscv-isa-manual-a18153d6f4c82e895fff7978d283aa2b231eb5e4.zip riscv-isa-manual-a18153d6f4c82e895fff7978d283aa2b231eb5e4.tar.gz riscv-isa-manual-a18153d6f4c82e895fff7978d283aa2b231eb5e4.tar.bz2 | |
Removed redundant text that LR can reserve a different subset on each invocation.
Diffstat (limited to 'src')
| -rw-r--r-- | src/a.tex | 4 |
1 files changed, 1 insertions, 3 deletions
@@ -185,9 +185,7 @@ not meet the forward-progress guarantee. An implementation can reserve an arbitrarily large subset of the address space on each LR, provided the memory range includes all bytes -of the addressed data word. The reserved address range does not have -to be constant on each dynamic invocation of a static LR instruction, -or on each time a given address and data word size are used by an LR. +of the addressed data word. An SC can only pair with the most recent LR in program order. An SC may succeed if no store from another hart to the address range reserved by the LR can be observed to have occurred between the LR and |