Specify synchronous exception priority ordering

Closes #327

2 files changed, 47 insertions, 0 deletions

diff --git a/src/machine.tex b/src/machine.tex
index e8b8c70..38e7022 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1953,6 +1953,52 @@ a policy on whether these need to be distinguished, and if so, whether
 a given opcode should be treated as illegal or privileged.
 \end{commentary}
 
+If an instruction raises multiple synchronous exceptions, the
+decreasing priority order of Table~\ref{exception-priority}
+indicates which exception is taken and reported in {\tt mcause}.
+The priority of any custom synchronous exceptions is implementation-defined.
+
+\begin{table*}[h!]
+\begin{center}
+\begin{tabular}{|r|l|}
+
+  \hline
+  Exception Code & Description \\
+  \hline
+  
+          3 & Instruction address breakpoint \\
+         12 & Instruction page fault \\
+          1 & Instruction access fault \\
+          2 & Illegal instruction \\   
+          0 & Instruction address misaligned \\
+   8, 9, 11 & Environment call \\
+          3 & Load/Store/AMO address breakpoint \\
+          6 & Store/AMO address misaligned \\
+          4 & Load address misaligned \\
+         15 & Store/AMO page fault \\
+         13 & Load page fault \\
+          7 & Store/AMO access fault \\
+          5 & Load access fault \\
+  \hline
+
+\end{tabular}
+\end{center}
+\caption{Synchronous exception priority in decreasing priority order.}
+\label{exception-priority}
+\end{table*}
+
+\begin{commentary}
+Instruction address breakpoints and data address breakpoints (a.k.a.
+watchpoints) have the same cause value but different priority.
+\end{commentary}
+
+\begin{commentary}
+Instruction address misaligned exceptions are raised by control-flow
+instructions with misaligned targets, rather than by the act of fetching an
+instruction.  Therefore, these exceptions have lower priority than other
+instruction address exceptions.
+\end{commentary}
+
 \subsection{Machine Trap Value ({\tt mtval}) Register}
 
 The {\tt mtval} register is an MXLEN-bit read-write register formatted as shown
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 74598b4..be185b9 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -31,6 +31,7 @@ The changes in this version of the document include:
 \item Added a draft proposal for a hypervisor extension.
 \item Specified which interrupt sources are reserved for standard use.
 \item Allocated some synchronous exception causes for custom use.
+\item Specified the priority ordering of synchronous exceptions.
 \item Added specification that xRET instructions may, but are not
   required to, clear LR reservations if A extension present.
 \item The virtual-memory system no longer permits supervisor mode to execute