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author | Andrew Waterman <andrew@sifive.com> | 2019-03-08 18:29:40 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-03-08 18:29:40 -0800 |
commit | ceb9d837f6377040f63ffd3b95eb86b139cb29ef (patch) | |
tree | 2e703ce0f840ac40f38c3ea8df9b512e0a03cc15 /src | |
parent | b53514acfee103f882c86352bc321cf777b06c26 (diff) | |
download | riscv-isa-manual-ceb9d837f6377040f63ffd3b95eb86b139cb29ef.zip riscv-isa-manual-ceb9d837f6377040f63ffd3b95eb86b139cb29ef.tar.gz riscv-isa-manual-ceb9d837f6377040f63ffd3b95eb86b139cb29ef.tar.bz2 |
SFENCE.VMA orders visible stores, not just local stores
Diffstat (limited to 'src')
-rw-r--r-- | src/supervisor.tex | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index ab406b1..bc9b15f 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -925,11 +925,11 @@ The supervisor memory-management fence instruction SFENCE.VMA is used to synchronize updates to in-memory memory-management data structures with current execution. Instruction execution causes implicit reads and writes to these data structures; however, these implicit references are ordinarily not -ordered with respect to loads and stores in the instruction stream. Executing -an SFENCE.VMA instruction guarantees that any stores in the instruction stream -prior to the SFENCE.VMA are ordered before all implicit references -to the memory-management data structures subsequent -to the SFENCE.VMA. Further details on the behavior of this instruction are +ordered with respect to explicit loads and stores. Executing +an SFENCE.VMA instruction guarantees that any previous stores already visible +to the current RISC-V hart are ordered before all subsequent implicit references +from that hart to the memory-management data structures. +Further details on the behavior of this instruction are described in Section~\ref{virt-control} and Section~\ref{pmp-vmem}. \begin{commentary} |