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author | Andrew Waterman <andrew@sifive.com> | 2019-04-11 13:52:20 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-04-11 13:52:20 -0700 |
commit | 30f01bd475a5dc0bc533c92f06cb329218ac5d76 (patch) | |
tree | 38c08402e9b822efceb5c8d2d617de0146f17cf9 /src | |
parent | 9b901e2679828849ebb63e4e358427212f37c849 (diff) | |
download | riscv-isa-manual-30f01bd475a5dc0bc533c92f06cb329218ac5d76.zip riscv-isa-manual-30f01bd475a5dc0bc533c92f06cb329218ac5d76.tar.gz riscv-isa-manual-30f01bd475a5dc0bc533c92f06cb329218ac5d76.tar.bz2 |
Explain when sideleg/sedeleg must exist
Closes #366
Diffstat (limited to 'src')
-rw-r--r-- | src/machine.tex | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 41298c3..a7a3ba6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1093,10 +1093,16 @@ S-mode or U-mode to the S-mode trap handler. If U-mode traps are supported, S-mode may in turn set corresponding bits in the {\tt sedeleg} and {\tt sideleg} registers to delegate traps that occur in U-mode to the U-mode trap handler. +In systems with S-mode, the {\tt medeleg} and {\tt mideleg} registers must +exist, whereas the {\tt sedeleg} and {\tt sideleg} registers should only exist +if the N extension for user-mode interrupts is also implemented. In systems with two privilege modes (M/U) and support for U-mode traps, setting a bit in {\tt medeleg} or {\tt mideleg} will delegate the corresponding trap in U-mode to the U-mode trap handler. +In systems with only M-mode and U-mode, the {\tt medeleg} and {\tt mideleg} +registers should only be implemented if the N extension for user-mode +interrupts is implemented. In systems with only M-mode, or with both M-mode and U-mode but without U-mode trap support, the {\tt medeleg} and {\tt mideleg} |