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| author | wmat <wmat@riscv.org> | 2024-03-19 14:48:12 -0400 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-03-19 14:48:12 -0400 |
| commit | f662bd20b0a57d4212efec376a0ec4da198c0f4a (patch) | |
| tree | 7e8d64f690ff174e4ebb03308bf663f8812f800f /src | |
| parent | 9dc9b5fa1ddf9fbf1d629fea4ec39a039db41353 (diff) | |
| download | riscv-isa-manual-f662bd20b0a57d4212efec376a0ec4da198c0f4a.zip riscv-isa-manual-f662bd20b0a57d4212efec376a0ec4da198c0f4a.tar.gz riscv-isa-manual-f662bd20b0a57d4212efec376a0ec4da198c0f4a.tar.bz2 | |
Fixed a couple of Notes
Adding the standard Note formatting.
Diffstat (limited to 'src')
| -rw-r--r-- | src/v-st-ext.adoc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index 0d569ec..1fc7279 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -5138,10 +5138,13 @@ FP32 and FP64). Vector single-width floating-point reductions (<<sec-vector-float-reduce>>) for EEW=32 and EEW=64 are supported as well as widening reductions from FP32 to FP64. -NOTE: As is the case with other RISC-V extensions, it is valid to +[NOTE] +==== +As is the case with other RISC-V extensions, it is valid to include overlapping extensions in the same ISA string. For example, RV64GCV and RV64GCV_Zve64f are both valid and equivalent ISA strings, as is RV64GCV_Zve64f_Zve32x_Zvl128b. +==== ==== Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point |