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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 18:51:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 18:51:49 -0700 |
| commit | fc5b6ca73edcb04f7c8d8f215ecf0d543466e6a0 (patch) | |
| tree | d158f2017e1c9dc411ad367b191a0b1f749a7257 /src | |
| parent | c9bfb416ea54c962c51ed4cd5955a1f638164cc5 (diff) | |
| download | riscv-isa-manual-fc5b6ca73edcb04f7c8d8f215ecf0d543466e6a0.zip riscv-isa-manual-fc5b6ca73edcb04f7c8d8f215ecf0d543466e6a0.tar.gz riscv-isa-manual-fc5b6ca73edcb04f7c8d8f215ecf0d543466e6a0.tar.bz2 | |
State endianness assumption of code example
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index ca3b543..be3413e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1679,8 +1679,9 @@ to the intermediate value of the comparand: sw a0, mtimecmp # New value. \end{verbatim} \end{center} -\caption{Sample code for setting the 64-bit time comparand in RV32 - assuming the registers live in a strongly ordered I/O region.} +\caption{Sample code for setting the 64-bit time comparand in RV32, assuming + a little-endian memory system and that the registers live in a strongly + ordered I/O region.} \label{mtimecmph} \end{figure} |