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| author | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 00:19:02 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 00:19:02 -0700 |
| commit | d725d8af2dfc8c637873a19e91ec4df747460eea (patch) | |
| tree | 5ee1dc7623d6f17e8c50d4ef5f19c57f91cbfa32 /src | |
| parent | 4eeaf69b4afcb711be566f98cbe19425c6a6cc49 (diff) | |
| download | riscv-isa-manual-d725d8af2dfc8c637873a19e91ec4df747460eea.zip riscv-isa-manual-d725d8af2dfc8c637873a19e91ec4df747460eea.tar.gz riscv-isa-manual-d725d8af2dfc8c637873a19e91ec4df747460eea.tar.bz2 | |
Don't mandate that multiple harts on a core share mcycle
The commentary indicates that sharing mcycle between harts is mandatory,
but I don't think that's a good idea -- both because it's introducing a
constraint that is very hard to formalize (ie, WTF is a core) and
because I think some systems will desire different behavior.
This patch softens the wording in the commentary to avoid the appearance
that sharing mcycle between threads is mandatory.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 9bbb48b..9416df9 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1922,7 +1922,7 @@ desirable to conditionally inhibit them to reduce energy consumption. Providing a single CSR to inhibit all counters also allows the counters to be atomically sampled. -As all the harts on a processor core share a {\tt cycle} counter, +As all the harts on a processor core may share a {\tt cycle} counter, so they share an {\tt mcountinhibit}.CY bit. Because the {\tt time} counter can be shared between multiple cores, it |