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author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 18:05:40 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 18:05:40 -0700 |
commit | c9bfb416ea54c962c51ed4cd5955a1f638164cc5 (patch) | |
tree | aaee3ed512eee65c99e59b3feb0299f8d8d328d6 /src | |
parent | a81b0a0cf2e2846a6af9f6a492780bec72baa5f3 (diff) | |
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Clarify sign of REM; add commentary
Closes #375
Diffstat (limited to 'src')
-rw-r--r-- | src/m.tex | 11 | ||||
-rw-r--r-- | src/preamble.tex | 1 |
2 files changed, 10 insertions, 2 deletions
@@ -98,8 +98,15 @@ MULDIV & divisor & dividend & DIV[U]W/REM[U]W & dest & OP-32 \\ DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of {\em rs1} by {\em rs2}, rounding towards zero. -REM and REMU provide the remainder of the -corresponding division operation. If both the quotient and remainder +REM and REMU provide the remainder of the corresponding division operation. +For REM, the sign of the result equals the sign of the dividend. + +\begin{commentary} +For both signed and unsigned division, it holds that +\mbox{$\textrm{dividend} = \textrm{divisor} \times \textrm{quotient} + \textrm{remainder}$}. +\end{commentary} + +If both the quotient and remainder are required from the same division, the recommended code sequence is: DIV[U] {\em rdq, rs1, rs2}; REM[U] {\em rdr, rs1, rs2} ({\em rdq} cannot be the same as {\em rs1} or {\em rs2}). Microarchitectures can diff --git a/src/preamble.tex b/src/preamble.tex index cb66be4..ed13e4e 100644 --- a/src/preamble.tex +++ b/src/preamble.tex @@ -15,6 +15,7 @@ \usepackage{comment} \usepackage{enumitem} \usepackage{verbatimbox} +\usepackage{amsmath} \usepackage[olditem,oldenum]{paralist} |